8.3.1.3.1 Power Up

If the AC, USB and BAT pin voltages are below the internal UVLO threshold V_UVLO (2.5 V typical) all IC blocks are disabled and the TPS65810 is not operational, with all functions OFF. When an external power source or battery with voltage greater than the V_UVLO voltage threshold is applied to AC/USB or BAT pins the internal TPS65810 references are powered up, biasing internal circuits. When all the main internal supply rails are active the TPS65810 I²C registers are set to the power-up default values, shown in Table 1.

After the internal I²C register power-up defaults are loaded the power path control logic is enabled, connecting the external power source to the OUT pin. A status flag (nRAMLOAD) is set to LO in the SOFT_RESET register, indicating that the I²C registers were loaded with the power-up defaults, and the TPS65810 enters the ENABLE state.

8.3.1.3.2 Enable

In the ENABLE mode the RESPWRON output is set to the LO level, the INT pin mode is set to high impedance and all the power-good comparators that monitor the integrated supply outputs are disabled. The ENABLE mode is used by the TPS65810 to detect when the main system power rail (OUT pin) is powered and ready to be used on the internal supply power-up. The OUT pin voltage is sensed by an internal low-system-voltage comparator which holds the IC in the ENABLE mode until the system power-bus voltage (OUT pin) has reached a minimum operating voltage, defined by the user. The internal comparator senses the system voltage at pin SYS_IN, and the threshold for the minimum system operating voltage at the OUT pin is set by the external divider connected from OUT pin to SYS_IN pin. The threshold voltage is calculated in Equation 1.

Equation 1.

where

• R6 and R1 are external resistors
• V_{(LOW_SYS)} = 1 V (typical)

The minimum system operating voltage must always be set above the internal UVLO threshold V_UVLO. In normal application conditions the minimum system operating voltage is usually set to a value that assures that the TPS65810 integrated regulators are not operating in the dropout region.

When the voltage at the SYS_IN pin exceeds the internal threshold V_{(LOW_SYS)} the TPS65810 device is ready to start the system power sequencing, and the SEQUENCING mode is entered.

8.3.1.3.3 Sequencing

The sequencing state starts immediately after the enable state. In this mode of operation the integrated supplies are turned ON. The TPS65810 sequencing timing diagram shown in Figure 18 details the internal timing delays and supply sequencing. At the end of the sequencing state the user-programmable reset timer is started, and the TPS65810 enters the reset state.

1. SM1 and SM2 are externally enabled by GPIO1 and GPIO2. This waveform represents the earliest time that SM1 and SM2 are enabled if GPIO1 and GPIO2 are tied high.

2. LDO5, SM1, and SM2 are all enabled at the same time. This waveform represents the earliest time that LDO5 is enabled if VIN_LDO35 is connected to OUT. LDO5 power up can be synchronized to SM1 or SM2 by connecting VIN_LDO35 to the SM1 or SM2 output, respectively.

Figure 18. TPS65810 Supply Sequencing Timing

8.3.1.3.4 Reset

When the reset state starts the RESPWRON output is LO. The user can program the reset timer value by selecting the value of the external capacitor connected to pin TRSTPWON, as shown in Equation 2.

The TPS65810 RESPWRON pin must be used to reset the external host. During the external host reset (RESPWRON = LO) the I²C SDA and SCL pins are not used to access TPS65810 internal registers. If a non-standard configuration is used to reset the system the SDA and SCL lines must not be used to communicate with the TPS65810 until RESPWRON = HI, to avoid overwriting the integrated power supply internal power-up settings during the sequencing mode.

The power-good comparators are masked during the reset mode. The reset mode ends when the reset timer expires, and the TPS65810 goes into the power-good check mode.

The RESPWRON signal set to a high level is the proper signal to use as an indicator that the device has transitioned out of the reset state. During the power-up sequence the RESPWRON pin is asserted LOW until the RESET TIMER expires. The RESET TIME (t_reset = 1ms/nF × CTRSTPWON) can be programmed through a capacitor between the TRSTPWON pin and ground.

When the RESPWRON signal is LO, all internal and external interrupts are ignored. As a result, the open-drain output that asserts the INT pin LO during a NORMAL MODE interrupt request is disabled. The INT pin is then asserted HI through a pullup resistor that is typically connected to VOUT. After the RESPWRON signal goes HI, the interrupt controller is given control of the INT pin. Finally, the rising edge of the RESPWRON pin must be used to indicate the PMIC has transitioned from the RESET STATE to the POWER-GOOD CHECK STATE. At that point, the interrupt controller asserts an interrupt if necessary.

8.3.1.3.5 Power-Good Check

In the power-good check mode the power-good comparators are enabled, providing status on the integrated supplies output voltages. An output voltage is considered as out of regulation and generates a fault condition if the output voltage is below 90% of the target output voltage regulation value. If a power-good fault is detected the SLEEP mode is set, if a power-good fault is not detected the NORMAL mode is set.

The individual supply power-good status can be masked through an I²C register PGOODFAULT_MASK. Supplies that have their power-good fault status masked do not generate a power-good fault. However, the status bit for the supply indicates that the output voltage is out of regulation.

The power-good mask register bits default to masked upon power up.

8.3.1.3.6 Sleep Mode

The SLEEP mode is set when a thermal fault or system low voltage fault is detected, under NORMAL operation mode set. This operation mode is also set when a power-good fault is detected during the power-good check state or the I²C bit SLEEP_MODE. In the SLEEP mode the RESPWRON output is set to LO, and the I²C registers keep the same contents as in the state preceding SLEEP mode, with the exception of the following control bits, which are reset to the default power-up values:

1. LDO1,2,3,4,5 and RTC_OUT are enabled, SIM LDO is disabled: EN_LDO register set to default values
2. LDO0 disabled, all GPIOs with no control function assigned: GPIO12, GPIO3 registers set to default values
3. White LED driver is set to OFF: SM3_SET register has all bits set to LO
4. RGB drivers are set to OFF: RGB_FLASH, RGB_RED, RGB_GREEN, RGB_BLUE registers are set to default values
5. PWM, PWM_LED drivers OFF: PWM, LED_PWM registers are set to default values
6. ADC engine reset to power-up default: ADC_SET, ADC_DELAY, ADC_WAIT registers are set to default values

At the end of the SLEEP mode, the sequencer block uses the I²C control register values (which were reset to the default power-up values) to sequence the integrated power supplies. The SLEEP mode ends when one of the three following events occurs:

1. If SLEEP was set by thermal fault: The SLEEP mode ends only when all external input supplies and battery pack are removed and a UVLO condition is detected by the TPS65810, setting the NO POWER mode.
2. If SLEEP was set by a system low voltage detection, or I²C bit SLEEP_MODE, only with battery present: Input power must be connected, setting the TPS65810 in the ENABLE mode. If no input power is inserted, the battery discharges until the TPS65810 detects a UVLO condition and enters the NO POWER mode.
3. If sleep was set by a system low voltage detection, power-good fault or SLEEP_MODE, with battery and input power present: all external input supplies connected to AC and USB pins must be removed, and then at least one of them reconnected to the system. The input power cycling triggers a transition from SLEEP mode to the ENABLE mode.

8.3.1.3.7 Normal Mode

If a power-good fault is not present at the end of the power-good check mode the NORMAL mode starts. In this mode of operation the I²C registers define the TPS65810 operation, and the host has full control on operation modes, parameter settings, and so forth. The normal state operation ends if a thermal fault, system low voltage fault (V(SYS_IN) < V_{LOW_SYS}) or power-good fault is detected. A thermal fault or system low voltage fault sets the SLEEP mode operation, a power-good fault sets the NO POWER operation mode. From the normal mode the converters SM1 and SM2 can be set in the STANDBY mode, with reduced output voltages. In NORMAL mode either an I²C register bit (SOFT_RESET register bit SOFT_RST) or a hardware input ( HOT_RESET pin set to LO) can trigger a transition to the RESET state, enabling implementation of a host reset function. In NORMAL mode an I²C register bit (SOFT_RESET register bit SLEEP_MODE) can trigger a transition to SLEEP mode.

8.3.1.3.8 Processor Standby State

This state is set using an I²C register or a GPIO configured as SM1 and SM2 stand-by control. In stand-by mode operation, the SM1 and SM2 voltages are set to value distinct than the normal mode output voltage, and SM1/SM2 are set to PFM mode. The stand-by output voltage is defined in I²C registers SM1_STANDBY and SM2_STANDBY.

Table 2. Interrupt Controller, Open-Drain Output (INT)

Table 3. Events Triggering TPS65810 Operating Mode Changes

8.3.2.2.1 Detecting the System Status

The power path and charge management block operate independently of the other TPS65810 circuits. Internal circuits check battery parameters (pack temperature, battery voltage, charge current) and system parameters (AC and USB voltage, battery voltage detection), setting the power path MOSFETs operating modes automatically. The TPS65810 has integrated comparators that monitor the battery voltage, AC pin voltage, USB pin voltage and the OUT pin voltage. The data generated by those comparators is used by the power path control logic to define which of the integrated power path switches are active. Figure 21 shows a simplified block diagram for the system status detection.

Figure 21. TPS65810 Systems Status Detection, Charger and Power Path Section

Table 4 lists the system power detection conditions. V_IN(DT), V_OUTSH, V_BATSH, V_OVP are the TPS65810 internal references, refer to the electrical characteristics in the Specifications section for additional details.

8.3.2.2.2 Power Path Logic: Priority Algorithm

The system power bus supply is automatically selected by the power path control logic, following an internal algorithm. The power path function detects an external input power connection when the input voltage exceeds the battery pack voltage. It also detects a supplement mode need (battery switch must be turned ON) when the system voltage (OUT pin) is below the battery voltage. A connected and non-selected external supply or the battery is automatically switched to the system bus, following the priority algorithm, when the external supply currently selected is disconnected from the system.

The input power priority is hard-wired internally, with the AC input having the higher priority, followed by the USB input (2^nd) and the battery pack (3^rd). Using the I²C CHG_CONFIG register control bit CE the user can override the power path algorithm, connecting the battery to the system power bus. Take care when using the battery-to-system connection option, as the system power bus is not connected back to the AC or USB inputs (even if those are detected) when the battery is removed. Table 5 describes the priority algorithm.

The power path status is stored in register CHG_STAT.

8.3.2.2.3 Input Current Limit

The USB input current is limited to the maximum value programmed by the host, using the I²C interface. If the system current requirements exceed the input current limit, the output voltage collapses, the charge current is reduced, and finally, the supplement mode is set. The input current limit value is set with the I²C charge control register bits PSEL and ISET2, and it is applied to the USB input ONLY. The AC input current limit is fixed to the internal short circuit limit value.

8.3.2.2.4 System Voltage Regulation

The system voltage is regulated to a fixed voltage when one of the input power supplies is connected to the system. The system voltage regulation is implemented by a control loop that modulates the selected switch Rds(on).

The typical system regulation voltage is 4.6 V.

8.3.2.2.5 Input Overvoltage Detection

The AC and USB input voltages are monitored by voltage comparators that identify an overvoltage condition. If an overvoltage condition is detected a status register bit is set, indicating a potential fault condition.

When an overvoltage condition is detected, the AC or USB switches state is not modified. If any of those switches was ON, it is kept in the ON state. During overvoltage conditions, the system voltage is still regulated, and no major safety issues are observed when not modifying the input switch state.

If the input overvoltage condition results in excessive power dissipation, the thermal shutdown circuit is activated, the AC and USB switches are turned OFF, and the BAT switch is turned ON.

8.3.2.2.6 Output Short-Circuit Detection

If the OUT pin voltage falls below an internal threshold V_INOUTSH the AC and USB switches are turned off and internal pullup resistors are connected from AC pin to OUT pin and USB pin to OUT pin. When the short circuit is removed those resistors enable the OUT pin voltage to rise above the V_INOUTSH threshold, returning the system to normal operation.

8.3.2.2.7 Battery Short-Circuit Detection

If the OUT pin voltage falls below the BAT pin voltage by more than an internal threshold V_BATOUTSH the battery switch is turned off and internal pullup resistor is connected between the OUT pin and the BAT pin. This resistor enables detection of the short removal, returning the system to normal operation.

8.3.2.2.8 Initial Power Path Operation

During the initial TPS65810 power-up the contents of the ISET2, CE and SUSPEND bits on the control register are immediately implemented. The charger is disabled (SUSPEND=LO) and the selected input current limit is set internally to 500 mA max.

8.3.2.2.9 No-Battery Detection Circuit

The ANLG1 pin may be used to detect the connection of an external resistor that is embedded in a battery pack and is used as a pack ID function. The ANLG1 pin has an internal current source connected between OUT and ANLG1, which is automatically enabled when the TPS65810 is not in SLEEP mode. The current levels for ANLG1 pin can be programmed through I²C register ADC_WAIT, bits BATID_n, as shown in Figure 22.

Figure 22. Battery Removal Detection, ANLG1 Pin

An internal comparator with a fixed deglitch time, t _DGL(NOBAT) monitors the ANLG1 pin voltage, if V(ANLG1) > V(OUT) – V_NOBATID, a battery removed condition is detected and an internal discharge switch is activated, connecting an internal resistor from BAT pin to AGND1. Note that ANLG1 can also be used as an analog input for the ADC converter, in this case the voltage at pin ANLG1 must never exceed the V(OUT) – V_NOBATID, threshold to avoid undesired battery discharge.

8.3.2.2.10 Using the Input Power to Run the System and Charge the Battery Pack

The external supply connected to AC or USB pins must be capable of supplying the system power and the charger current. If the external supply power is not sufficient to run the system and charge the battery pack the TPS65810 executes a two-stage algorithm that prevents a low voltage condition at the system power bus:

1. The charge current is reduced, until the total (charger + system current) is at a level that can be supplied by the external input supply. This function is implemented by a dedicated charger control loop (see Dynamic Power Path Management for additional details).
2. The battery switch is turned ON if the charge current is reduced to zero and the input current is not enough to run the system. In this mode of operation both the battery and the external input power supply the system power ( supplement operation mode).

The supplement operation mode is automatically set by the TPS65810 when the input power is switched to the OUT pin, and the OUT pin voltage falls below the battery voltage.

8.3.2.3.1 Operating Modes

The TPS65810 supports charging of single-cell Li-Ion or Li-Pol battery packs. The charge process is executed in three phases: precharge (or preconditioning), constant current and constant voltage.

The charge parameters are selectable through I²C interface and using external components. The charge process starts when an external input power is connected to the system, the charger is enabled by the I²C register CHG_CONFIG bits CE = HI and CHGON = HI, and the battery voltage is below the recharge threshold, V(BAT) < V_(RCH). When the charge cycle starts a safety timer is activated. The safety timer timeout value is set by an external resistor connected to the TMR pin.

When the charger is enabled two control loops modulate the battery switch drain to source impedance to limit the BAT pin current to the programmed charge current value (charge current loop) or to regulate the BAT pin voltage to the programmed charge voltage value (charge voltage loop). If V(BAT) < 3 V (typical) the BAT pin current is internally set to 10% of the programmed charge current value. Figure 23 shows a typical charge profile for an operation condition that does not cause the IC junction temperature to exceed 125°C (typical).

Figure 23. Typical Charge Cycle, Thermal Loop not Active

If the operating conditions cause the IC junction temperature to exceed 125°C the charge cycle is modified, with the activation of the integrated thermal control loop. The thermal control loop is activated when an internal voltage reference, which is inversely proportional to the IC junction temperature, is lower than a fixed, temperature stable internal voltage. The thermal loop overrides the other charger control loops and reduces the charge current until the IC junction temperature returns to 125°C, effectively regulating the IC junction temperature.

Figure 24 shows a modified charge cycle, with the thermal loop active.

Figure 24. Typical Charge Cycle, Thermal Loop Active

8.3.2.3.2 Battery Preconditioning

The TPS65810 applies a precharge current I_o(PRECHG) to the battery if the battery voltage is below the V_(LOWV) threshold, preconditioning deeply discharged cells. The charge current loop regulates the ISET1 pin voltage to an internal reference value, V_(PRECHG). The resistor connected between the ISET1 and AGND pins, R_SET, determines the precharge rate.

The precharge rate programmed by R_SET is always applied to a deeply discharged battery pack, independently of the input power selection (AC or USB). Use Equation 3 to calculate the precharge current.

Equation 3.

where

• K_(SET) is the charge current scaling factor
• V_(PRECHG) is the precharge set voltage

8.3.2.3.3 Constant Current Charging

The constant charge current mode (fast charge) is set when the battery voltage is higher than the precharge voltage threshold. The charge current loop regulates the ISET1 pin voltage to an internal reference value, V_SET. The fast charge current regulation point is defined by the external resistor connected to the ISET1 pin, R_SET, as shown in the following:

Equation 4.

where

• V_(SET) (2.5 V typical) is the voltage at ISET1 pin during charge current regulation
• K_(SET) = charge- current scaling factor

The reference voltage V_(SET) can be reduced through I²C register CHG_CONFIG bits ISET1_1 and ISET1_0. V_(SET) can be selected as a percentage (75%, 50% or 25%) of the original 2.5 V typ, non-attenuated V_(SET) value, effectively scaling down the charge current.

The ISET1 resistor always sets the maximum charge current if the AC input is selected. When the USB input is selected, the maximum charge current is defined by the USB input current limit and the programmed charge current. If the USB input current limit is lower than the I_O(OUT) value, the battery switch is set in the dropout region and the charge current is defined by the input current limit value and system load, as shown in Figure 25.

Figure 25. Input Current Limit Impact on Effective Charge Current

8.3.2.3.4 Charge Termination and Recharge

The TPS65810 monitors the charging current during the voltage regulation phase. Charge is terminated when the charge current is lower than an internal threshold, set to 10% (typical) of the fast charge current rate. The termination point applies to both AC and USB charging. Use Equation 5 to calculate the termination point, I_(TERM).

Equation 5.

where

• V_(TERM) is the termination detection voltage reference

The voltage at ISET1 pin is monitored to detect termination, and termination is detected when V(SET1) < V_(TERM) (0.25 V typical). The voltage reference V_(TERM) is internally set to 10% of the V_(SET) reference voltage, and it is modified if the reference voltage V_(SET) is scaled through I²C register CHG_CONFIG bits ISET1_1 and ISET1_0. V_(TERM) is reduced by the same percentage used to scale down V_(SET).

Table 7 lists the charge current and termination thresholds for a 1-A charge current set (1-kΩ resistor connected to ISET1 pin), with the selected input current limit set to a value higher than the programmed charge current. The termination current is scaled for all charge current modes (AC or USB), as it is always set by the ISET1 pin external resistor value.

When the termination is detected, a new charge cycle starts if the voltage on the BAT pin falls below the V_(RCH) threshold. A new charge start is also triggered if the charger is enabled, disabled, or re-enabled through I²C (CHG_CONFIG register bits CE or CHGON), or if both AC and USB input power are removed and then at least one of them is re-inserted.

The termination is disabled when the thermal loop OR DPPM loop are active, and during supplement mode.

8.3.2.3.5 Battery Voltage Regulation, Charge Voltage

The voltage regulation feedback is Implemented by sensing the BAT pin voltage, which is connected to the positive side of the battery pack. The TPS65810 monitors the battery-pack voltage between the BAT and AGND1 pins, when the battery voltage rises to the V_O(REG) threshold the voltage regulation phase begins and the charging current tapers down.

The charging voltage can be selected as 4.2 V or 4.365 V (typical). The default power-up voltage is 4.2 V. As a safety measure the 4.365 V charge voltage is programmed only if two distinct bits are set through I²C: VCHG=HI in the CHG_CONFIG, and CHG_VLTG=LO in the GPIO3 register.

8.3.2.3.6 Temperature Qualification

The TPS65810 charger section does not monitor the battery temperature. This function may be implemented by an external host, which can measure the pack temperature by monitoring the ADC channel connected to the TS pin. An external pullup resistor must be connected to the TS pin to bias the pack thermistor, as the TPS65810 device has no internal current source connected to the TS pin.

8.3.2.3.7 Dynamic Power Path Management

Under normal operating conditions, the OUT pin voltage is regulated when the AC or USB pin is powering the OUT pin and the battery pack is being charged. If the total (system + charge current) exceeds the available input current, the system voltage drops below the regulation value.

The dynamic power path management function monitors the system output voltage. A condition where the external input supply rating has been exceeded or the input current limit has been reached is detected when the OUT pin voltage drops below an user-defined threshold, V_DPPM. Use Equation 6 to calculate the value of V_DPPM.

Equation 6.

where

• R_DPPM = external resistor connected to DPPM pin
• K_DPPM = DPPM scaling factor
• I_DPPM = DPPM pin internal current source

To correct this situation the DPPM loop reduces the charge current, regulating the OUT pin voltage to the user-defined V_DPPM threshold. The DPPM loop effectively identifies the maximum current that can be delivered by the selected input and dynamically adjusts the charge current to guarantee that the end equipment is always powered. To minimize OUT voltage ripple during DPPM operation the V_DPPM threshold must be set just below the system regulation voltage.

If the charge current is reduced to zero by the DPPM and the input current is still lower than the OUT pin load, the output voltage falls below the DPPM threshold, decreasing until the battery supplement mode is set
[V(OUT) = V(BAT) – V_SUP(DT) ].

8.3.2.3.8 Charger Off Mode

The TPS65810 charger circuitry enters the low-power OFF mode if both AC and USB power are not detected. This feature prevents draining the battery during the absence of input supply.

8.3.2.3.9 Precharge Safety Timer

The TPS65810 device activates an internal safety timer during the battery preconditioning phase. The precharge safety timer time-out value is set by the external resistor connected to TMR pin, RTMR, and the timeout constants K_PRE and K_TMR. Use Equation 7 to calculate the timeout value value of the precharge safety timer.

The K_PRE constant typical value is 0.1, setting the precharge timer value to 10% of the charge safety timer value.

When the charger is in suspend mode, set through I²C register CHG_CONFIG bit CHGON or set by a pack temperature fault, the precharge safety timer is put on hold (that is, charge safety timer is not reset). Normal operation resumes when the charger exits the suspend mode. If V(BAT) does not reach the internal voltage threshold V_PRECHG within the precharge timer period a fault condition is detected and the charger is turned off.

If the TMR pin is left floating, an internal resistor of 50 KΩ (typical) is used to generate the time base used to set the precharge timeout value. The typical precharge timeout value can be then calculated using Equation 8.

8.3.2.3.10 Charge Safety Timer

As a safety mechanism the TPS65810 has a user-programmable timer that measures the total fast charge time. This timer (charge safety timer) is started at the end of the preconditioning period. The safety charge timeout value is set by the value of an external resistor connected to the TMR pin R_TMR). Use Equation 9 to calculate the charge safety timer time-out value.

When the charger is in suspend mode, set through I²C register CHG_CONFIG bit CHGON or set by a pack temperature fault, the charge safety timer is put on hold (that is, charge safety timer is not reset). Normal operation resumes when the charger exits the suspend mode. If charge termination is not reached within the timer period a fault condition is detected, and the charger is turned off.

The charge safety timer is held in reset if the TMR pin is left floating. Under this mode of operation an internal resistor, 50 kΩ typical, sets the internal charger and power path deglitch and delay times, as well as the precharge safety timer timeout value.

8.3.2.3.11 Timer Fault Recovery

The TPS65810 provides a recovery method to deal with timer fault conditions. The following summarizes this method:

• Condition 1: Charge voltage above recharge threshold, V_(RCH), and timeout fault occurs.

• Condition 2: Charge voltage below recharge threshold,V_(RCH), and timeout fault occurs.

All timers are reset and all timer fault conditions are cleared when a new charge cycle is started either through I²C (toggling CHG_CONFIG bits CE, CHGON) or by cycling the input power. All timers are reset and all timer fault conditions are cleared when the TPS65810 enters the UVLO mode.

8.3.2.3.12 Dynamic Timer Function

The charge and precharge safety timers are programmed by the user to detect a fault condition if the charge cycle duration exceeds the total time expected under normal conditions. The expected total charge time is usually calculated based on the fast charge current rate.

When the thermal loop or the DPPM loops are activated the charge current is reduced, and a false safety timer fault can be observed if this mode of operation is active for a long periods. To avoid this undesirable fault condition the TPS65810 activates the dynamic timer function when the DPPM and thermal loops are active. The dynamic timer function slows down the safety timers clock, effectively adding an extra time to the programmed timeout value as follows:

1. If the battery voltage is below the battery depleted threshold: the precharge timer value is modified while the thermal loop or the DPPM loop are active
2. If the battery voltage is above the precharge threshold: the safety timer value is modified if the DPPM or the thermal loop are active AND the battery voltage is below the recharge threshold.

The TPS65810 dynamic timer function circuit monitors the voltage at pin ISET1 during precharge and fast charge. When the charger is regulating the charge current, the voltage at pin ISET1 is regulated by the control loops to either V_(SET) or V_(PRECHG). If the thermal loop or DPPM loops are active, the voltage at pin ISET1 is lower than V_(SET) or V_PRECHG, and the dynamic timer control circuit changes the safety timers clock period based on the V_(SET)/V(ISET1) ratio (fast charge) or V_(PRECHG)/V(ISET1) ratio (precharge).

The maximum clock period is internally limited to twice the value of the programmed clock period, which is defined by the resistor connected to TMR pin, as shown in Figure 26.

Figure 26. Safety Timer Internal Clock Slowdown

The effective charge safety timer value can then be expressed as follows:

Effective precharge timeout = t_(PRECHG) + t_(PCHGADD)

Effective charge safety timeout = t_(CHG) + t_(CHGADD)

The added timeout values, t_(PCHGADD), t_(CHGADD), are equal to the sum of all time periods when either the thermal loop or DPPM loops were active. The maximum added timeout value is internally limited to 2 × t_(CHG) or 2 × t_(PRECHG)

Table 8. Charge Management

Table 9. Power Path Management

Table 10. Selectable Output Voltage LDO

Table 11. Programmable Output Voltage LDO

Table 12. Fixed-Output Voltage LDOs

Table 13. Buck Converters, I²C Programmable Output Voltage

Table 14. ADC Input Channel Overview

8.3.5.3.1 ADC Conversion Cycle

A conversion cycle includes all the steps required to successfully sample the selected input signal and transfer the converted data to the I²C, generating an interrupt request to the host ( pin: HI→LO). The number of individual conversions (samples) in a conversion cycle is defined by the I²C ADC_SET register bits READ_MODE settings, and can range from a single sample to 256 samples. The conversion cycle settings for the ALU is defined by register ADC_READING and it can be set to average, maximum value detection, minimum value detection or no processing (ADC engine output loaded in the accumulator directly).

The conversion cycle begins with the first sampling and ends when the following occurs:

• The required ALU operations are performed on the final sample, and
• The ALU accumulator data is transferred to the I²C ADC_READING register, and
• The register bit ADC_STATUS in the ADC_READING register is set to LO.

A conversion cycle is always started by the external host when the ADC_EN bit in the ADC_SET register is toggled from LO to HI by a I²C write operation. Resetting the ADC_EN bit to LO before the current conversion cycle ends (INT: LO → HI, ADC_STATUS bit set to LO) is not recommended, as the ADC keeps its current configuration until the current conversion cycle ends.

At the end of a conversion cycle the output data is stored at registers in the ALU block. The ADC_STATUS bit is set to LO ( DONE ) and an interrupt is generated (INT pin: HI→LO ) if the ADC_STATUS bit is unmasked, at the interrupt masking registers INT_MASK. It must be noted that the minimum, maximum and average values are ALWAYS calculated by the ALU for each conversion cycle.

The value loaded in the I²C registers ADC READING_HI and ADC READING_LO at the end of a conversion cycle is defined by control bits ADC_READ0 and ADC_READ1 in register ADC READING_HI. The average, minimum, maximum, and last-sample values for a conversion cycle can be read if the external host executes an I²C write operation, changing the values of bits ADC_READ0 and ADC_READ1, followed by an I²C read operation on registers ADC READING_HI and ADC READING_LO. The minimum, maximum, average, and last values have the same value if a conversion cycle with only one sample is executed.

The ADC_READ0 and ADC_READ1 bits can not be modified during the execution of a conversion cycle. A new conversion cycle must be started only after the current conversion cycle is completed, by toggling the ADC_EN bit from HI to LO and HI again.

8.3.5.3.2 External Trigger Operation

The trigger control circuit can be programmed to use an external signal to start a conversion. The TPS65810 GPIO3 input is configurable as an ADC trigger, with ADC conversion starting on either a rising edge or falling edge. When using an external trigger the trigger delay, trigger wait time delay and trigger hold-off mode can be programmed using I²C registers.

The procedure to start an externally-triggered conversion cycle has the following steps:

1. Verify that the current conversion cycle has ended (ADC_STATUS = LO, I²C register ADC_READING_HI)
2. Set ADC_EN = LO
3. Configure ADC sampling mode, ALU mode, trigger parameters, and so forth
4. Set ADC_EN = HI

After step 4 the ADC is armed, waiting for an external trigger detection to start a conversion cycle. Similarly to the non-triggered mode, the ADC configuration must not be modified until the current conversion cycle ends. Note that in the external trigger mode the current cycle does not end if the converter is armed and an external trigger is not detected.

8.3.5.3.3 Detecting an External Trigger Event

An external trigger event is detected when the GPIO3 input has an edge that matches the edge detection programmed in the EDGE bit, at the I²C register ADC_DELAY. The internal ADC trigger can be delayed with respect to the external trigger signal edge. The delay time value is set by the ADC_DELAY register bits DELAY_n, and can range from 0 μs (no delay) to 750 μs. A conversion is started only if the external trigger remains at its active level when the delay time expires, as shown in Figure 37. In a positive-edge detection the active trigger level is HI; in a negative-edge detection the active trigger level is LO.

Figure 37. ADC Conversion Triggered by GPIO3 Positive Edge Triggered Active Level Hi

8.3.5.3.4 Executing Multiple-Sample Cycles With an External Trigger

When executing conversion cycles that require multiple samples it may be desirable to synchronize the input signal conversion using either an external trigger that has a periodic repetition rate or an external asynchronous trigger that indicates when the external input signal being converted is valid. The TPS65810 has additional operating modes and timing parameters that can be programmed using the I²C to configure multiple sample conversion cycles.

In multiple sample cycles the host can select the wait time between samples using the bits WAITn in the ADC_WAIT register to set the wait time between samples. The wait time is measured between the end of a conversion and the start of a new conversion.

With the default power-up settings (HOLDOFF=LO, ADC_DELAY register), the TPS65810 executes a multiple-sample conversion cycle if the first sample is taken when the trigger is at its active level. Subsequent samples are converted at the end of the wait time, even if the trigger returns to the non-active level. The external trigger level edge is ignored until the current conversion cycle ends.

Figure 38. ADC Conversion Triggered by GPIO3 Positive Edge Triggered Active Level Hi, Holdoff = LC

If the sample conversion needs to be synchronized with an external trigger, during multiple sample conversion cycles, the control bit HOLDOFF must be set to HI. When the holdoff mode is active, the internal trigger starts a sample conversion only if the external trigger was detected and is at its active level at the end of the wait time, as shown in Figure 39.

Figure 39. ADC Conversion Triggered by GPIO3 Positive Edge Triggered Active Level HI,
Holdoff = HI, Four Sample Cycles

When the multiple sample cycles are executed the host must configure the maximum and minimum limits for the ADC output using registers DLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. A conversion cycle ends if any individual conversion result exceeds the maximum limit value or is below the minimum limit value. When an out of limit conversion is detected an interrupt is sent to the host, and the ADC_STATUS bit on register ADC READING_HI is set to DONE.

8.3.5.3.5 Continuous Conversion Operation (Repeat Mode)

The TPS65810 ADC can be set to operate in a continuous conversion mode, with back-to-back conversion cycles executed. The REPEAT mode is targeted at applications where an input is continuously monitored for a period of time, and the host must be informed if the monitored input is out of the range set by I²C registers DLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. In REPEAT mode each conversion is started when the ADC trigger (internal or external) is detected, and a new conversion cycle is started when the current conversion cycle ends. All the trigger and sampling modes available for normal conversion cycles are available in repeat mode. Executing I²C read operations to get the ADC readings for average, minimum, maximum and last sample values is possible in REPEAT mode. However, TI does not recommend this operation, as the REPEAT mode does not generate a DONE status flag making it difficult to synchronize the ADC data reading to the end of a conversion cycle.

TI recommends using these steps for the REPEAT mode:

1. Configure the ADC conversion cycle: trigger mode, sample mode, select input signal, or others.
2. Configure the HI and LO limits for the ADC readings
3. Set the ADC_DELAY register bit REPEAT to HI
4. Toggle ADC_DELAY register bit ADC_EN bit from LO to HI
5. Monitor the INT pin. An interrupt triggered by ADC_STATUS = LO indicates that the selected input signal is out of range

To exit the continuous mode the host must follow the steps below, if external trigger mode was set:

1. Exit external trigger mode
2. Set REPEAT bit to LO, effectively terminating the repeat mode. This generates an additional conversion; at the end of this conversion the ADC is ready for a new configuration.
3. Set ADC_EN to LO after on-going conversion ends.

To exit the continuous mode the host must follow the steps below, if internal trigger mode was set:

1. Set REPEAT bit to LO, effectively terminating the repeat mode.
2. Set ADC_EN to LO, after on-going conversion ends

8.3.5.3.6 ADC Input Signal Range Setting

The registers DHILIMn and DLOLIMn can be used by the host to set maximum and minimum limits for the DAC engine output. At the end of each conversion the ADC output is checked for the maximum and minimum limits, and a status flag is set if the converted data exceeds the high limit or is under the low limit. In multiple sample operation the converted data range is checked when all programmed samples have been converted.

The host can mask or unmask interrupts caused by the ADC range status bits using the INT_MASKn registers.

8.3.5.3.7 ADC State Machine

Figure 40 shows the ADC state machine with all the trigger and operation modes.

Figure 40. Trigger and Operation Modes for the ADC State Machine

Table 15. 10-Bit Successive Approximation ADC

8.3.6.1.1 SM3 Control Logic Overview

The SM3 boost converter operates in a pulse frequency modulation (PFM) scheme with constant peak current control. This control scheme maintains high efficiency over the entire load current range and enables the use of small external components, as the switching frequency can reach up to 1 MHz depending on the load conditions. The LED current ripple is defined by the external inductor size.

The converter monitors the sense voltage at pin FB3, and turns on the integrated power stage switch when V_(FB3) is below the 250-mV (typical) internal reference voltage and the LED Switch is ON, starting a new cycle. The integrated power switch turns off when the inductor current reaches the internal 500-mA (typical) peak current limit, or if the switch is on for a period longer than the maximum on-time of 6 μs (typical). The integrated power switch also turns off when the LED switch is set to OFF. As the integrated power switch is turned off, the external Schottky diode is forward biased, delivering the stored inductor energy to the output. The main switch remains off until the FB3 pin voltage is below the internal 250-mV reference voltage and the LED switch is turned ON, when it is turned on again.

This PFM peak current control scheme sets the converter in discontinuous conduction mode (DCM), and the switching frequency depends on the inductor, input/output voltage and LED current. Lower LED currents reduce the switching frequency, with high efficiency over the entire LED current range. This regulation scheme is inherently stable, allowing a wide range for the selection of the inductor and output capacitor.

8.3.6.1.2 Peak Current Control (Boost Converter)

The SM3 integrated power stage switch is turned on until the inductor current reaches the DC current limit I_MAX(L3) (500 mA, typical). Because of internal delays, typically around 100 ns, the actual current exceeds the DC current limit threshold by a small amount. Use Equation 12 to calculate the typical peak current limit.

Equation 12.

The current overshoot is directly proportional to the input voltage, and inversely proportional to the inductor value.

8.3.6.1.3 Soft-Start

All inductive step-up converters exhibit high in-rush current during start-up. If no special precautions are taken, voltage drops can be observed at the input supply rail during start-up, with unpredictable results in the overall system operation.

The SM3 boost converter limits the inrush current during start-up by increasing the current limit in the following three steps:

1. 125 mA (typical),
2. 250 mA (typical) and
3. 500 mA (typical)

The two initial steps (125 mA and 250 mA) are active for 256 power stage switching cycles.

8.3.6.1.4 Enabling the SM3 Converter

The SM3_SET I²C register controls the SM3 LED-switch duty cycle. If the register is set to all zeros SM3 is set to OFF mode. When the host writes a value other than 00 in SM3_SET the SM3 converter is enabled, entering the soft-start phase and then normal operation. The SM3 converter can operate with duty cycles varying from 0.4% to 99.6%, with LED switch frequencies of 122 Hz or 180 Hz. The LED switch operating frequency is set by bit SM3_LF, in the SOFT_RESET register.

8.3.6.1.5 Overvoltage Protection

The output voltage of the boost converter is sensed at pin SM3, and the integrated power stage switch is turned OFF when V(SM3) exceeds the internal overvoltage threshold V_OVP3. The converter returns to normal operation when V(SM3) < V_OVP3 – V_HYS(OVP3).

8.3.6.1.6 Under Voltage Lockout Operation

When the TPS65810 device enters the UVLO mode, the SM3 converter is set to OFF mode with the power stage MOSFET switch and the LED switch open (off).

8.3.6.1.7 Thermal Shutdown Operation

When the TPS65810 device enters the thermal shutdown mode, the SM3 converter is set to OFF mode with the power stage MOSFET switch and the LED switch open (off).

8.3.6.2.1 PWM Pin Driver

The TPS65810 device offers one low-frequency, open-drain PWM driver, capable of driving up to 150 mA. The PWM frequency and duty cycle are defined by the PWM I²C register settings. The PWM parameters are set in I²C register PWM. Available frequency values range from 500 Hz to 15 kHz, with 8 frequency values and 16 duty cycle options (6.25% each).

8.3.6.2.2 LED_PWM Pin Driver

The TPS65810 has another PWM driver output (pin LED_PWM), which is optimized to drive a backlight LED. The LED_PWM driver controls the external LED current intensity using a pulse-width control method, with duty cycle being set by the I²C register LED_PWM.

The pulse width method implemented generates a burst of high frequency pulses, with a pattern that is repeated periodically. For a duty cycle of 50%, all of the high -frequency pulses have a 50% duty cycle. The duty cycle control sets individual pulses to 100% duty cycle when increasing the LED_PWM output duty cycle; for decreasing LED_PWM output duty cycles individual pulses are set to 0% duty cycle. An example of distinct duty cycles is shown in Figure 44; the sum of the individual pulses on/off time over the repetition period is equivalent to the duty cycle obtained with traditional single-pulse duty cycle circuits.

Figure 44. Example of Distinct Duty Cycles

The repetition period can be set using the register SOFT_RESET control bit SM3_LF_OSC to either 180 Hz (HI) or 122 Hz (LO). Each repetition period has a total of 256 pulses, enabling a resoltuion of 0.4% when programming the duty cycle. The LED_SET register enables control of the duty cycle through I²C, with duty cycle ranging from 0.4% to 99.6%. Setting the LED_SET register to all zeros forces the LED_PWM pin to 0% duty cycle (OFF).

8.3.6.2.3 RGB Driver

The TPS65810 has a dedicated driver for an RGB external LED. Three outputs are available (pins RED, GREEN, BLUE), with common settings for operation mode (flash on/off, flash period, flash on time), LED current and phase delay between outputs. The TPS65810 RGB driver continually flashes the external LEDs connected to the RED, GREEN and BLUE pins using the flash operation parameters defined in register RGB_FLASH.

The currents for the external LEDs can be programmed through I²C, and external resistors are not required to limit the LED current. However, they can be added to set the LED current if the available I²C values are not compatible with the current application, as shown in Figure 45.

Figure 45. Limiting the External LED Current

The flashing-mode parameters defined in register RGB_FLASH enable setting the flashing period from 1 to 8 seconds in 0.5-sec steps, or to continuous operation. Flashing operation is enabled by setting the FLASH_EN bit in register RGB_FLASH to HI. This bit must be set HI to enable the RGB current-sink channels.

Each driver has an individual duty cycle control. The duty cycle modulation method used is similar to the PWM_LED duty cycle control, with high frequency pulses being generated when the driver (RED, GREEN, or BLUE pins) is ON. The repetition period for the RGB drivers has a total of 32 pulses, enabling a 3.125% resolution when programming the individual RED, GREEN and BLUE drivers duty cycles. The duty cycles for each driver can be set individually using control bits on registers RGB_RED, RGB_GREEN and RGB_BLUE.

The RGB drivers can be programmed to sink 4, 8, or 12 mA, with no external current limiting resistor.

Table 16. White Led Constant Current Driver

Table 17. Open-Drain PWM Drivers

Table 18. RGB Open-Drain LED Driver

Table 19. SM3 Duty Cycle Settings

Table 20. RGB Duty Cycle Control Settings

Table 21. PWM Frequency and Duty Cycle Settings

Table 22. GPIO Commands and I²C Registers Commands

8.3.7.2.1 GPIO Configuration Table

Table 23 lists the I²C register settings required to program the available GPIO modes. The GPIO pins logic level is available at register SM1_STANDBY, bits B5, B6 and B7.

Table 24. GPIO3 Functions

Table 25. GPIO2 Functions

Table 26. GPIO1 Functions

Table 27. TPS65810 I²C Read and Write Address

Table 28. I²C Naming Conventions Used

Table 1. Valid Write Sequence Address Registers

Table 2. One-Byte Write Address Register

Table 3. Valid Read Sequence ACK Register

Table 4. Valid Read Sequence Address Registers

Table 5. Incremental Read Sequences

Table 6. START and Non-HA0 or Non-HA1 Address

Table 7. Attempt to Specify Non-Allowed READ Address

Table 8. Attempt to Specify Non-Allowed WRITE Address