SLVSCJ5B December   2015  – June 2020 TPS7H3301-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Standard DDR Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT/VO Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD/VIN Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VIN Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to
    0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference
    • ±15-mV accuracy
    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated