UCC27524A-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results
- Device Temperature Grade 1
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C4B
- Industry-Standard Pin Out
- Two Independent Gate-Drive Channels
- 5-A Peak Source and Sink-Drive Current
- Independent Enable Function for Each Output
- TTL and CMOS-Compatible Logic Threshold
Independent of Supply Voltage - Hysteretic-Logic Thresholds for High-Noise
Immunity - Ability to Handle Negative Voltages (–5 V) at
Inputs - Inputs and Enable Pin-Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage - 4.5-V to 18-V Single-Supply Range
- Outputs Held Low During VDD-UVLO, (ensures
glitch-free operation at power-up and power-
down) - Fast Propagation Delays (13-ns typical)
- Fast Rise and Fall Times (7-ns and 6-ns typical)
- 1-ns Typical Delay Matching Between 2-Channels
- Ability to Parallel Two Outputs for High-Drive
Current - Outputs Held in LOW When Inputs are Floating
- SOIC-8 and MSOP-8 PowerPad™ Package Options
- Operating Temperature Range of –40°C to 140°C
The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle 5 V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.
For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.
The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN) packages.
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技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | データシート | UCC27524A-Q1 Dual 5-A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability データシート (Rev. B) | PDF | HTML | 2015年 7月 24日 | ||
アプリケーション・ノート | Why use a Gate Drive Transformer? | PDF | HTML | 2024年 3月 4日 | |||
アプリケーション概要 | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||||
アプリケーション概要 | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||||
その他の技術資料 | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 2018年 10月 29日 | ||||
ホワイト・ペーパー | Driving the future of HEV/EV with high-voltage solutions (Rev. B) | 2018年 5月 16日 | ||||
技術記事 | Are you on-board? Demystifying EV charging systems | PDF | HTML | 2017年 7月 31日 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
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PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®
設計とシミュレーション向けの環境である PSpice for TI (...)
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パッケージ | ピン数 | ダウンロード |
---|---|---|
HVSSOP (DGN) | 8 | オプションの表示 |
SOIC (D) | 8 | オプションの表示 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 材質成分
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点
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