DP83867ERGZ-R-EVM

The DP83867ERGZ-R-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports the RGMII MAC interface.

The DP83867ERGZ-R-EVM evaluation module (EVM) for the DP83867 device includes 3 on-board status LEDs and 5-V connectors with onboard LDO regulators. The EVM is JTAG accessible and can provide a 125-MHz reference clock from an on-board 25-MHz crystal. The serial management interface, MDIO/MDC, is supported and can be used to access the PHY registers for additional features. The 4-level straps let you configure the system without the need to directly access the PHY registers. External power supplies can be connected to each specified voltage rail for additional system evaluation. The DP83867 EVM supports wake-on-LAN, start-of-frame detect IEEE 1588 timestamp and configurable I/O voltages.

特長

イーサネット PHY