- DRV8x06x-Q1EVM & DRV8705x-Q1EVM User’s Guide
(PDF 2842 KB)
2019年 2月 6日 （英語）
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The DRV8106S-Q1EVM is designed to evaluate the DRV8106S-Q1, which is an integrated, automotive qualified brushed DC motor driver. The DRV8106S-Q1 is a highly integrated half-bridge gate driver, capable of driving high-side and low-side N-channel power MOSFETs. It generates the proper gate drive voltages using an integrated doubler charge pump for the high-side and a linear regulator for the low-side.
The device uses a smart gate drive architecture to reduce system cost and improve reliability. The gate driver optimizes dead time to avoid shoot-through conditions, provides control to decreasing electromagnetic interference (EMI) through adjustable gate drive current, and protects against drain to source and gate short conditions with VDS and VGS monitors.
A wide common mode shunt amplifier provides inline current sensing to continuously measure motor current.
The DRV8106S-Q1 provide an array of protection features to ensure robust system operation. These include under and overvoltage monitors for the power supply and charge pump, VDS overcurrent and VGS gate fault monitors for the external MOSFETs, offline open load and short circuit diagnostics, and internal thermal warning and shutdown protection.
The DRV8106S-Q1EVM has an half-bridge consisting of two N-channel MOSFETs that drive motors bi-directionally at up to 15-A RMS, 20-A peak current. The EVM operates from a single power supply for the analog power and from the USB line for the digital power, which can be customized to be externally supplied. A negative 18 V reverse baterry protection circuit, along with a 20 A RMS rated PI filter are provided to clean up the power supply input and protect against incorrect battery connections.
- Half-bridge smart gate driver EVM for automotive applications
- Temperature grade 1: –40°C to +125°C, TA
- 4.9-V to 37-V operating range
- Doubler charge pump for 100% PWM
- Half-bridge control mode
- SPI interface for detailed configuration and diagnostics
- Smart gate drive architecture
- Adjustable slew rate control
- 0.5-mA to 62-mA peak source current output
- 0.5-mA to 62-mA peak sink current output
- Integrated dead-time handshaking
- MOSFET drain to source and gate monitors
- Wide common mode current shunt amplifier
- Inline sensing
- Adjustable gain settings (10, 20, 40, 80 V/V)
- Integrated feedback resistors
- Adjustable PWM blanking scheme
- Integrated protection features
- Dedicated driver disable pin (drvoff)
- Supply and regulator voltage monitors
- MOSFET VDS overcurrent monitors
- MOSFET VGS gate fault monitors
- Charge pump for reverse polarity MOSFET
- Offline open load and short circuit diagnostics
- Device thermal warning and shutdown
- Fault condition interrupt pin (nFAULT)