AFE7422 14 ビット 9GSPS DAC / 3GSPS ADC 搭載デュアルチャネル RF サンプリング AFE の評価モジュール
- AFE7444/22 User's Guide
(PDF 8033 KB)
2018年 10月 10日 （英語）
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The AFE7422 evaluation module (EVM) is an RF-sampling transceiver platform that can be configured to support up to two-transmit and two-receive (2T2R) channels simultaneously. The module evaluates the AFE7422 device, which is a dual-channel RF-sampling analog front end (AFE) with 14-bit 9-GSPS digital-to-analog converters (DACs), 14-bit 3-GSPS analog-to-digital converters (ADCs), and on-chip integrated PLL/VCO for high-frequency clock generation for DACs and ADCs.
AFE7422EVM has options to use dual digital up converters and down converters in each channel to synthesize and digitize multiple wideband signals with high dynamic range simultaneously. On-chip integrated digital step attenuator (DSA) for the receiver channels and DSA-equivalent functionality for the transmitter channels are supported. Eight JESD204B-compatible serializer/deserializer (SerDes) transceivers running up to 15 Gbps can be used for providing inputs and outputs to/from the AFE7422 device through the onboard FMC connector.
AFE7422EVM includes the LMK04828 clock generator for providing a reference signal to the AFE on-chip PLL and for generating the required SYSREF signals for the JESD204B protocol. Also included is the option for providing an ultra-low-phase noise external clocking solution.
AFE7422EVM implements an efficient low-dropout (LDO)-less power-management solution using only DC-DC converters for the required power rails. The design interfaces with the TI pattern/capture card solution (TSW14J57EVM), as well as many FPGA development kits.
- Allows evaluation of 4T4R RF-sampling AFE7422 solutions
- JESD204B data interface to simplify digital interface; compliant up to 15-Gbps lane rates
- Supports JESD204B subclass 1 for synchronization and compatibility
- Option for DC-DC-based LDO-less power-management solution
- Onboard clocking solution supported with LMK04828 and for generating SYSREF
- On-chip interpolation/decimation filter inputs/outputs sample data at reduced sample rates and improved SNR