SNAS791D
December 2019 – February 2022
LMK1C1102
,
LMK1C1103
,
LMK1C1104
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Fail-Safe Inputs
9.4
Device Functional Modes
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Receiving Notification of Documentation Updates
13.2
Support Resources
13.3
Trademarks
13.4
Electrostatic Discharge Caution
13.5
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DQF|8
MPSS009B
PW|8
MPDS568
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snas791d_oa
snas791d_pm
1
Features
High-performance 1:2, 1:3 or 1:4 LVCMOS clock buffer
Very low output skew < 50 ps
Extremely low additive jitter < 50 fs maximum
7.5 fs typical at V
DD
= 3.3 V
10 fs typical at V
DD
= 2.5 V
19.2 fs typical at V
DD
= 1.8 V
Very low propagation delay < 3 ns
Synchronous output enable
Supply voltage: 3.3 V, 2.5 V, or 1.8 V
3.3-V tolerant input at all supply voltages
Fail-safe inputs
f
max
= 250 MHz for 3.3 V
f
max
= 200 MHz for 2.5 V and 1.8 V
Operating temperature range: –40°C to 125°C
Available in 8-pin TSSOP package
Available in 8-pin WSON package