SCPS269 September   2017 TIC12400

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7  Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch inputs Settings
        1. 8.3.8.1 Input Current Source/Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable/disable And Interrupt generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix Polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
      1. 8.6.1  DEVICE_ID register (Offset = 1h) [reset = 20h]
      2. 8.6.2  INT_STAT Register (Offset = 2h) [reset = 1h]
      3. 8.6.3  CRC Register (Offset = 3h) [reset = FFFFh]
      4. 8.6.4  IN_STAT_MISC Register (Offset = 4h) [reset = 0h]
      5. 8.6.5  IN_STAT_COMP Register (Offset = 5h) [reset = 0h]
      6. 8.6.6  IN_STAT_ADC0 Register (Offset = 6h) [reset = 0h]
      7. 8.6.7  IN_STAT_ADC1 Register (Offset = 7h) [reset = 0h]
      8. 8.6.8  IN_STAT_MATRIX0 Register (Offset = 8h) [reset = 0h]
      9. 8.6.9  IN_STAT_MATRIX1 Register (Offset = 9h) [reset = 0h]
      10. 8.6.10 ANA_STAT0 Register (Offset = Ah) [reset = 0h]
      11. 8.6.11 ANA_STAT1 Register (Offset = Bh) [reset = 0h]
      12. 8.6.12 ANA_STAT2 Register (Offset = Ch) [reset = 0h]
      13. 8.6.13 ANA_STAT3 Register (Offset = Dh) [reset = 0h]
      14. 8.6.14 ANA_STAT4 Register (Offset = Eh) [reset = 0h]
      15. 8.6.15 ANA_STAT5 Register (Offset = Fh) [reset = 0h]
      16. 8.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]
      17. 8.6.17 ANA_STAT7 Register (Offset = 11h) [reset = 0h]
      18. 8.6.18 ANA_STAT8 Register (Offset = 12h) [reset = 0h]
      19. 8.6.19 ANA_STAT9 Register (Offset = 13h) [reset = 0h]
      20. 8.6.20 ANA_STAT10 Register (Offset = 14h) [reset = 0h]
      21. 8.6.21 ANA_STAT11 Register (Offset = 15h) [reset = 0h]
      22. 8.6.22 ANA_STAT12 Register (Offset = 16h) [reset = 0h]
      23. 8.6.23 CONFIG Register (Offset = 1Ah) [reset = 0h]
      24. 8.6.24 IN_EN Register (Offset = 1Bh) [reset = 0h]
      25. 8.6.25 CS_SELECT Register (Offset = 1Ch) [reset = 0h]
      26. 8.6.26 WC_CFG0 Register (Offset = 1Dh) [reset = 0h]
      27. 8.6.27 WC_CFG1 Register (Offset = 1Eh) [reset = 0h]
      28. 8.6.28 CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]
      29. 8.6.29 CCP_CFG1 Register (Offset = 20h) [reset = 0h]
      30. 8.6.30 THRES_COMP Register (Offset = 21h) [reset = 0h]
      31. 8.6.31 INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]
      32. 8.6.32 INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]
      33. 8.6.33 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
      34. 8.6.34 INT_EN_CFG1 Register (Offset = 25h) [reset = 0h]
      35. 8.6.35 INT_EN_CFG2 Register (Offset = 26h) [reset = 0h]
      36. 8.6.36 INT_EN_CFG3 Register (Offset = 27h) [reset = 0h]
      37. 8.6.37 INT_EN_CFG4 Register (Offset = 28h) [reset = 0h]
      38. 8.6.38 THRES_CFG0 Register (Offset = 29h) [reset = 0h]
      39. 8.6.39 THRES_CFG1 Register (Offset = 2Ah) [reset = 0h]
      40. 8.6.40 THRES_CFG2 Register (Offset = 2Bh) [reset = 0h]
      41. 8.6.41 THRES_CFG3 Register (Offset = 2Ch) [reset = X]
      42. 8.6.42 THRES_CFG4 Register (Offset = 2Dh) [reset = X]
      43. 8.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [reset = 0h]
      44. 8.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [reset = 0h]
      45. 8.6.45 THRESMAP_CFG2 Register (Offset = 30h) [reset = 0h]
      46. 8.6.46 Matrix Register (Offset = 31h) [reset = 0h]
      47. 8.6.47 Mode Register (Offset = 32h) [reset = 0h]
    7. 8.7 Programming Guidelines
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Digital IO Switches and Analog Voltage Monitoring
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Operates with Supply Voltage (VS) from 6.5 V to 35 V with Over-voltage and Under-voltage Warning
  • Monitors up 24 Direct Switch Inputs with 10 Inputs Configurable to Monitor Switches Connected to Either Ground or Supply
  • Switch Input Withstands 40 V and Reverse Supply Condition Down to -24 V
  • 6 Configurable Wetting Current Settings:
    (0 mA, 1 mA, 2 mA, 5 mA, 10 mA, and 15 mA)
  • Integrated 10-bit ADC for Multi-Position Analog Switch Monitoring
  • Integrated Comparator with 4 Programmable Threshold for Input Monitoring
  • Ultra-low Operating Current in Polling Mode:
    68 μA Typical (tPOLL = 64 ms, tPOLL_ACT = 128 μs,
    All 24 Inputs Active, Comparator Mode, All Switches Open)
  • Interfaces Directly to MCU Using 3.3 V/5 V Serial Peripheral Interface (SPI) Protocol
  • Interrupt Generation to Support Wake-Up Operation on All Inputs
  • Integrated Supply and Temperature Sensing
  • ±8 kV Contact Discharge ESD Protection on Input Pins per IEC 61000-4-2 With Appropriate External Components
  • 38-Pin TSSOP Package

2 Applications

  • Signal Measurement
  • PLC, DCS and PAC
  • Instrumentation

3 Description

The TIC12400 is an advanced Multiple Switch Detection Interface (MSDI) device designed to detect external switch statuses. The TIC12400 supports 24 direct inputs, with 10 inputs configurable to monitor digital I/O switches. 6 wetting current settings can be programmed for each input to support different application scenarios. The TIC12400 features an integrated 10-bit ADC to monitor multi-position analog switches and a comparator to monitor digital switches independently of the MCU. The device supports wake-up operation on all switch inputs to eliminate the need to keep the MCU active continuously, thus reducing power consumption of the system. The TIC12400 supports 2 modes of operations: continuous and polling mode. In continuous mode, wetting current is supplied continuously. In polling mode, wetting current is turned on periodically to sample the input status based on a programmable timer, thus the system power consumption is significantly reduced. The TIC12400 also offers various fault detection and diagnostic features for improved system robustness.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TIC12400 TSSOP (38) 9.70 mm x 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TIC12400 App_diagram.gif