SCAS901D September   2010  – November 2017 CDCLVD1212

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Features

  • 2:12 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in
    10-kHz to 20-MHz
  • Low Output Skew of 35 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM

Applications

  • Telecommunications and Networking
  • Medical Imaging
  • Test and Measurement Equipment
  • Wireless Communications
  • General-Purpose Clocking

Description

The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1212 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1212 is packaged in small, 40-pin, 6-mm × 6-mm VQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCLVD1212 VQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Example

CDCLVD1212 app_cir_FP_cas901.gif