SCAS640G July   2000  – August 2016 CDCVF2505

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): < |150 ps|
    (Over 66 MHz to 200 MHz Range)
  • Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin TSSOP and 8-Pin SOIC Packages
  • Consumes Less Than 100 mA (Typical) in Power-Down Mode
  • Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
  • 25-Ω On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the Need for External Components

2 Applications

  • Synchronous DRAMs
  • Industrial Applications
  • General-Purpose Zero-Delay Clock Buffers

3 Description

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.

The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCVF2505 SOIC (8) 4.90 mm × 3.90 mm
TSSOP (8) 4.40 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

CDCVF2505 b0246-01_cas640.gif