Design Goals

Design Description

This application brief shows how to implement a simple rad-tolerant circuit that detects an over-current event caused by a single-event latch-up (SEL), in systems where not all other components SEL immune up to the target LET. This solution uses one comparator with a rail-to-rail input common mode range to create an over-current alert (OC-Alert) signal at the comparator output (COMP OUT) if the load current rises above 1A. The OC-Alert signal in this implementation is active low. So when the 1A threshold is exceeded, the comparator output goes low. Hysteresis is implemented such that OC-Alert will return to a logic high state when the load current reduces to 0.5A (a 50% reduction). This circuit uses an open-collector output comparator in order to level shift the output high logic level for controlling a digital logic input pin. For applications needing to drive the gate of a MOSFET switch, a comparator with a push-pull output is preferred.

Design Steps

1. Select value of R₆ so V_SHUNT is at least 10x greater than the comparator input offset voltage (V_IO). Note that making R₆ very large will improve OC detection accuracy but will reduce supply headroom.
   Equation 1. $V_{\mathrm{SHUNT}}=\left(I_{\mathrm{OC}}{R}_6\right)\ge 10V_{\mathrm{IO}}=55\mathrm{mV}$
   Equation 1. $\mathrm{set} R_6=100\mathrm{m\Omega } \mathrm{for} I_{\mathrm{OC}}=1A \& V_{\mathrm{IO}}=5.5\mathrm{mV}$
2. Determine the desired switching thresholds for when the comparator output will transition from high-to-low (V_L) and low-to-high (V_H). V_L represents the threshold when the load current crosses the OC level, while V_H represents the threshold when the load current recovers to a normal operating level.
   Equation 1. $V_L=V_S-\left(I_{\mathrm{OC}}{R}_6\right)=10-(1\times 0.1)=9.9V$
   Equation 1. $V_H=V_S-\left(I_{\mathrm{RC}}{R}_6\right)=10-(0.5\times 0.1)=9.95V$
   
3. With the non-inverting input pin of the comparator labeled as V_TH and the comparator output in a logic low state (ground), derive an equation for V_TH where V_H represents the load voltage (V_LOAD) when the comparator output transitions from low to high. Note that the simplified diagram for deriving the equation shows the comparator output as ground (logic low).
   
   Equation 1. $V_{\mathrm{TH}}=V_H\left(\frac{R_2}{R_1+R_2}\right)$
4. With the non-inverting input pin of the comparator labeled as V_TH and the comparator output in a high-impedance state, derive an equation for V_TH where V_L represents the load voltage (V_LOAD) when the comparator output transitions from high to low. Applying "superposition" theory to solve for V_TH is recommended.
   
   Equation 1. $V_{\mathrm{TH}}=V_L\left(\frac{R_2+R_3}{R_1+R_2+R_3}\right)+V_{\mathrm{PU}}\left(\frac{R_1}{R_1+R_2+R_3}\right)$
5. Eliminate variable V_TH by setting the two equations equal to each other and solve for R₁. The result is the following quadratic equation. Solving for R₂ is less desirable since there are more standard values for small resistor values than the larger ones.
   Equation 1. $0=V_{\mathrm{PU}}{R_1}^2+[V_{\mathrm{PU}}{R}_2+V_L(R_3+R_2)-V_H{R}_2]R_1+(V_L-V_H)[{R_2}^2+(R_2{R}_3\left)\right]$
6. Select values for R3 and R2. Please note that R₃ is significantly smaller than R₂ (R₃<<R₂). Increasing R₃ will cause the comparator logic high output level to increase beyond V_PU and should be avoided. For example, increasing R₃ to a value of 100k can cause the logic high output to be 3.6 V. In this case, we can select R₂ = 2M and R₃ = 1k.
   
   Equation 1. $R_2 = 2\mathrm{M\Omega }$
   Equation 1. $R_3 = 1\mathrm{k\Omega }$
7. Calculate R₁ after substituting in numeric values for V_PU, R₂, V_L, V_H, and R₃. For this design, set V_PU = 3.3, R₂ = 2M, V_L = 9.9, V_H = 9.95, and R₃ = 1k.
   Equation 1. $0= 3.3{R_1}^2+(6.591M)R_1-(200.1G)$
   Equation 1. $\mathrm{the} \mathrm{positive} \mathrm{root} \mathrm{for} R_1=29.9\mathrm{k\Omega }$
   Equation 1. $\mathrm{using} \mathrm{standard} 1\% \mathrm{resistor} \mathrm{values}, R_1=30.1\mathrm{k\Omega }$
8. Calculate V_TH using the equation derived in Design Step 3; use the calculated value for R₁. Note that V_TH is less than V_L since V_PU is less that V_L.
   Equation 1. $V_{\mathrm{TH}}=V_H\left(\frac{R_2}{R_1+R_2}\right)=9.802V$
9. With the inverting terminal labeled as V_TH, derive an equation for V_TH in terms of R₄, R₅, and V_S.
   Equation 1. $V_{\mathrm{TH}}=V_S\left(\frac{R_5}{R_4+R_5}\right)$
10. Calculate R₄ after substituting in numeric values R₅=1M, V_S=10, and the calculated value for V_TH.
    Equation 1. $R_4=\left(\frac{R_5(V_S-V_{\mathrm{TH}})}{V_{\mathrm{TH}}}\right)=20.15\mathrm{k\Omega }$
    Equation 1. $\mathrm{using} \mathrm{standard} 1\% \mathrm{resistor} \mathrm{values}, R_4=20.5\mathrm{k\Omega }$

Design Simulations

Transient Simulation Results

Design References

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

See Circuit SPICE Simulation File SBOMBL5, http://www.ti.com/lit/zip/sbombl5.

Design Featured Comparator