SPRUIU1C
July 2020 – February 2024
DRA821U
,
DRA821U-Q1
1
Read This First
About This Manual
Related Documentation From Texas Instruments
Support Resources
Glossary
Export Control Notice
Trademarks
1
Introduction
1.1
Device Overview
1.2
Device Block Diagram
1.3
Device Main Domain
1.3.1
Arm Cortex-A72 Subsystem
1.3.2
Arm Cortex-R5F Processor
1.3.3
Navigator Subsystem
1.3.4
Region-based Address Translation Module
1.3.5
Multicore Shared Memory Controller
1.3.6
DDR Subsystem
1.3.7
General Purpose Input/Output Interface
1.3.8
Inter-Integrated Circuit Interface
1.3.9
Improved Inter-Integrated Circuit Interface
1.3.10
Multi-channel Serial Peripheral Interface
1.3.11
Universal Asynchronous Receiver/Transmitter
1.3.12
Gigabit Ethernet Switch
1.3.13
Peripheral Component Interconnect Express Subsystem
1.3.14
Universal Serial Bus (USB) Subsystem
1.3.15
SerDes
1.3.16
General Purpose Memory Controller with Error Location Module
1.3.17
Multimedia Card/Secure Digital Interface
1.3.18
Enhanced Capture Module
1.3.19
Enhanced Pulse-Width Modulation Module
1.3.20
Enhanced Quadrature Encoder Pulse Module
1.3.21
Controller Area Network
1.3.22
Audio Tracking Logic
1.3.23
Multi-channel Audio Serial Port
1.3.24
Timers
1.3.25
Internal Diagnostics Modules
1.4
Device MCU Domain
1.4.1
MCU Arm Cortex-R5F Processor
1.4.2
MCU Region-based Address Translation Module
1.4.3
MCU Navigator Subsystem
1.4.4
MCU Analog-to-Digital Converter
1.4.5
MCU Inter-Integrated Circuit Interface
1.4.6
MCU Improved Inter-Integrated Circuit Interface
1.4.7
MCU Multi-channel Serial Peripheral Interface
1.4.8
MCU Universal Asynchronous Receiver/Transmitter
1.4.9
MCU Gigabit Ethernet Switch
1.4.10
MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
1.4.11
MCU Controller Area Network
1.4.12
MCU Timers
1.4.13
MCU Internal Diagnostics Modules
1.5
Device WKUP Domain
1.5.1
WKUP Device Management and Security Controller
1.5.2
WKUP General Purpose Input/Output Interface
1.5.3
WKUP Inter-Integrated Circuit Interface
1.5.4
WKUP Universal Asynchronous Receiver/Transmitter
1.5.5
WKUP Internal Diagnostics Modules
1.6
Device Identification
2
Memory Map
2.1
MAIN Domain Memory Map
2.2
MCU Domain Memory Map
2.3
WKUP Domain Memory Map
2.4
Processors View Memory Map
2.5
Region-based Address Translation
3
System Interconnect
3.1
System Interconnect Overview
3.2
System Interconnect Integration
3.2.1
Interconnect Integration in WKUP Domain
3.2.2
Interconnect Integration in MCU Domain
3.2.3
Interconnect Integration in MAIN Domain
3.3
System Interconnect Functional Description
3.3.1
Master-Slave Connections
3.3.2
Quality of Service (QoS)
3.3.3
Route ID
3.3.4
Initiator-Side Security Controls and Firewalls
3.3.4.1
Initiator-Side Security Controls (ISC)
3.3.4.1.1
Special System Level Priv-ID
3.3.4.1.2
Priv ID and ISC Assignment
3.3.4.2
Firewalls (FW)
3.3.4.2.1
Peripheral Firewalls (FW)
3.3.4.2.2
Memory or Region-based Firewalls
3.3.4.2.2.1
Region Based Firewall Functional Description
3.3.4.2.3
Channelized Firewalls
3.3.4.2.3.1
Channelized Firewall Functional Description
3.3.5
Null Error Reporting
3.3.6
VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
3.3.6.1
Overview and Feature List
3.3.6.1.1
Features Supported
3.3.6.1.2
Features Not Supported
3.3.6.2
Functional Description
3.3.6.2.1
Functional Operation
3.3.6.2.1.1
Overview
3.3.6.2.1.2
FIFOs
3.3.6.2.1.3
ID Allocator
3.3.6.2.1.4
Timer
3.3.6.2.1.5
Timeout Queue
3.3.6.2.1.6
Write Scoreboard
3.3.6.2.1.7
Read Scoreboard
3.3.6.2.1.8
Flush Mode
3.3.6.2.1.9
Flushing
3.3.6.2.1.10
Timeout Error Reporting
3.3.6.2.1.11
Command Timeout Error Reporting
3.3.6.2.1.12
Unexpected Response Reporting
3.3.6.2.1.13
Latency and Stalls
3.3.6.2.1.14
Bypass
3.3.6.2.1.15
Safety
3.3.6.3
Interrupt Conditions
3.3.6.3.1
Transaction Error Interrupt
3.3.6.3.1.1
Transaction Timeout
3.3.6.3.1.2
Unexpected Response
3.3.6.3.1.3
Command Timeout
3.3.6.4
Memory Map
3.3.6.4.1
Revision Register (Base Address + 0x00)
3.3.6.4.2
Configuration Register (Base Address + 0x04)
3.3.6.4.3
Info Register (Base Address + 0x08)
3.3.6.4.4
Enable Register (Base Address + 0x0C)
3.3.6.4.5
Flush Register (Base Address + 0x10)
3.3.6.4.6
Timeout Value Register (Base Address + 0x14)
3.3.6.4.7
Timer Register (Base Address + 0x18)
3.3.6.4.8
Error Interrupt Raw Status/Set Register (Base Address + 0x20)
3.3.6.4.9
Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
3.3.6.4.10
Error Interrupt Mask Set Register (Base Address + 0x28)
3.3.6.4.11
Error Interrupt Mask Clear Register (Base Address + 0x2C)
3.3.6.4.12
Timeout Error Info Register (Base Address + 0x30)
3.3.6.4.13
Unexpected Response Info Register (Base Address + 0x34)
3.3.6.4.14
Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
3.3.6.4.15
Error Transaction Tag/CommandID Register (Base Address + 0x3C)
3.3.6.4.16
Error Transaction Bytecnt Register (Base Address + 0x40)
3.3.6.4.17
Error Transaction Upper Address Register (Base Address + 0x44)
3.3.6.4.18
Error Transaction Lower Address Register (Base Address + 0x48)
3.3.6.5
Integration Overview
3.3.6.5.1
Parameterization Requirements
3.3.6.6
I/O Description
3.3.6.6.1
Clockstop Idle
3.3.6.6.2
Flush
3.3.6.6.3
Module I/O
3.3.6.7
User’s Guide
3.3.6.7.1
Programmer’s Guide
3.3.6.7.1.1
Initialization
3.3.6.7.1.2
Software Flush
3.3.7
Timeout Gasket (TOG)
3.4
System Interconnect Registers
3.4.1
QoS Registers
3.4.2
Firewall Exception Registers
3.4.3
Firewall Region Registers
3.4.4
Null Error Reporting Registers
4
Initialization
4.1
Initialization Overview
4.1.1
ROM Code Overview
4.1.2
Bootloader Modes
4.1.3
Terminology
4.2
Boot Process
4.2.1
MCU ROM Code Architecture
4.2.1.1
Main Module
4.2.1.2
X509 Module
4.2.1.3
Buffer Manager Module
4.2.1.4
Log and Trace Module
4.2.1.5
System Module
4.2.1.6
Protocol Module
4.2.1.7
Driver Module
4.2.2
DMSC ROM Description
4.2.3
Boot Process Flow
4.2.4
MCU Only vs Normal Boot
4.3
Boot Mode Pins
4.3.1
MCU_BOOTMODE Pin Mapping
4.3.2
BOOTMODE Pin Mapping
4.3.2.1
Primary Boot Mode Selection
4.3.2.2
Backup Boot Mode Selection When MCU Only = 0
4.3.2.3
Primary Boot Mode Configuration
4.3.2.4
Backup Boot Mode Configuration
4.3.3
No-boot/Dev-boot Configuration
4.3.4
Hyperflash Boot Device Configuration
4.3.5
OSPI Boot Device Configuration
4.3.6
QSPI Boot Device Configuration
4.3.7
SPI Boot Device Configuration
4.3.8
xSPI Boot Device Configuration
4.3.9
I2C Boot Device Configuration
4.3.10
MMC/SD Card Boot Device Configuration
4.3.11
eMMC Boot Device Configuration
4.3.12
Ethernet Boot Device Configuration
4.3.13
USB Boot Device Configuration
4.3.14
PCIe Boot Device Configuration
4.3.15
UART Boot Device Configuration
4.3.16
PLL Configuration
4.3.16.1
MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
4.3.16.2
MCU_PLL1
4.3.16.3
Main PLL1
4.3.16.4
Main PLL2
4.3.16.5
HSDIV Values
4.3.16.6
190
4.4
Boot Parameter Tables
4.4.1
Common Header
4.4.2
PLL Setup
4.4.3
PCIe Boot Parameter Table
4.4.4
I2C Boot Parameter Table
4.4.5
OSPI/QSPI/SPI Boot Parameter Table
4.4.6
Ethernet Boot Parameter Table
4.4.7
USB Boot Parameter Table
4.4.8
MMCSD Boot Parameter Table
4.4.9
UART Boot Parameter Table
4.4.10
Hyperflash Boot Parameter Table
4.5
Boot Image Format
4.5.1
Overall Structure
4.5.2
X.509 Certificate
4.5.3
Organizational Identifier (OID)
4.5.4
X.509 Extensions Specific to Boot
4.5.4.1
Boot Info (OID 1.3.6.1.4.1.294.1.1)
4.5.4.2
Image Integrity (OID 1.3.6.1.4.1.294.1.2)
4.5.5
Extended Boot Info Extension
4.5.5.1
Impact on HS Device
4.5.5.2
Extended Boot Info Details
4.5.5.3
Certificate / Component Types
4.5.5.4
Extended Boot Encryption Info
4.5.5.5
Component Ordering
4.5.5.6
Memory Load Sections Overlap with Executable Components
4.5.5.7
Device Type and Extended Boot Extension
4.5.6
Generating X.509 Certificates
4.5.6.1
Key Generation
4.5.6.1.1
Degenerate RSA Keys
4.5.6.2
Configuration Script
4.5.7
Image Data
4.6
Boot Modes
4.6.1
I2C Bootloader Operation
4.6.1.1
I2C Initialization Process
4.6.1.1.1
Block Size
4.6.1.1.2
226
4.6.1.2
I2C Loading Process
4.6.1.2.1
Loading a Boot Image From EEPROM
4.6.2
SPI Bootloader Operation
4.6.2.1
SPI Initialization Process
4.6.2.2
SPI Loading Process
4.6.3
QSPI Bootloader Operation
4.6.3.1
QSPI Initialization Process
4.6.3.2
QSPI Loading Process
4.6.4
OSPI Bootloader Operation
4.6.4.1
OSPI Initialization Process
4.6.4.2
OSPI Loading Process
4.6.5
PCIe Bootloader Operation
4.6.5.1
PCIe Initialization Process
4.6.5.2
PCIe Loading Process
4.6.6
Ethernet Bootloader Operation
4.6.6.1
Ethernet Initialization Process
4.6.6.2
Ethernet Loading Process
4.6.6.2.1
Ethernet Boot Data Formats
4.6.6.2.1.1
Limitations
4.6.6.2.1.2
BOOTP Request
4.6.6.2.1.2.1
MAC Header (DIX)
4.6.6.2.1.2.2
IPv4 Header
4.6.6.2.1.2.3
UDP Header
4.6.6.2.1.2.4
BOOTP Payload
4.6.6.2.1.2.5
TFTP
4.6.6.3
Ethernet Hand Over Process
4.6.7
USB Bootloader Operation
4.6.7.1
USB-Specific Attributes
4.6.7.1.1
DFU Device Mode
4.6.8
MMCSD Bootloader Operation
4.6.9
UART Bootloader Operation
4.6.9.1
Initialization Process
4.6.9.2
UART Loading Process
4.6.9.2.1
UART XMODEM
4.6.9.3
UART Hand-Over Process
4.7
Boot Memory Maps
4.7.1
Memory Layout/MPU
4.7.2
Global Memory Addresses Used by ROM Code
4.7.3
Memory Reserved by ROM Code
5
Device Configuration
5.1
Control Module (CTRL_MMR)
5.1.1
WKUP_CTRL_MMR0
5.1.1.1
WKUP_CTRL_MMR0 Overview
5.1.1.2
WKUP_CTRL_MMR0 Integration
5.1.1.3
WKUP_CTRL_MMR0 Functional Description
5.1.1.3.1
Description for WKUP_CTRL_MMR0 Register Types
5.1.1.3.1.1
Pad Configuration Registers
5.1.1.3.1.2
Kick Protection Registers
5.1.1.3.1.3
WKUP_CTRL_MMR0 Module Interrupts
5.1.1.3.1.4
Clock Selection Registers
5.1.1.3.1.5
Device Feature Registers
5.1.1.3.1.6
POK Module Registers
5.1.1.3.1.7
Power and Reset Related Registers
5.1.1.3.1.8
PRG Related Registers
5.1.1.3.1.9
Voltage Glitch Detect Control and Status Registers
5.1.1.3.1.10
I/O Debounce Control Registers
5.1.1.4
WKUP_CTRL_MMR0 Registers
5.1.2
MCU_CTRL_MMR0
5.1.2.1
MCU_CTRL_MMR0 Overview
5.1.2.2
MCU_CTRL_MMR0 Integration
5.1.2.3
MCU_CTRL_MMR0 Functional Description
5.1.2.3.1
Description for MCU_CTRL_MMR0 Register Types
5.1.2.3.1.1
Kick Protection Registers
5.1.2.3.1.2
MCU_CTRL_MMR0 Module Interrupts
5.1.2.3.1.3
Inter-processor Communication Registers
5.1.2.3.1.4
Timer I/O Muxing Control Registers
5.1.2.3.1.5
Clock Muxing and Division Registers
5.1.2.3.1.6
MCU_CPSW0 MAC Address Registers
5.1.2.4
MCU_CTRL_MMR0 Registers
5.1.2.5
MCU_SEC_MMR0_DBG_CTRL Registers
5.1.2.6
MCU_SEC_MMR0_BOOT_CTRL Registers
5.1.3
CTRL_MMR0
5.1.3.1
CTRL_MMR0 Overview
5.1.3.2
CTRL_MMR0 Integration
5.1.3.3
CTRL_MMR0 Functional Description
5.1.3.3.1
Description for CTRL_MMR0 Register Types
5.1.3.3.1.1
Pad Configuration Registers
5.1.3.3.1.2
Kick Protection Registers
5.1.3.3.1.3
CTRL_MMR0 Module Interrupts
5.1.3.3.1.4
Inter-processor Communication Registers
5.1.3.3.1.5
Timer I/O Muxing Control Registers
5.1.3.3.1.6
EHRPWM/EQEP Control and Status Registers
5.1.3.3.1.7
Clock Muxing and Division Registers
5.1.3.3.1.8
Ethernet Port Operation Control Registers
5.1.3.3.1.9
SERDES Lane Function Control Registers
5.1.3.3.1.10
DDRSS Dynamic Frequency Change Registers
5.1.3.4
CTRL_MMR0 Registers
5.1.3.5
SEC_MMR0_DBG_CTRL Registers
5.1.3.6
SEC_MMR0_BOOT_CTRL Registers
5.2
Power
5.2.1
Power Management Overview
5.2.2
Power Management Subsystems
5.2.2.1
Power Subsystems Overview
5.2.2.1.1
POK Overview
5.2.2.1.2
PRG / PRG_PP Overview
5.2.2.1.3
POR Overview
5.2.2.1.4
POK / PRG(_PP) /POR Overview
5.2.2.1.5
Timing
5.2.2.1.6
Restrictions
5.2.2.2
Power System Modules
5.2.2.2.1
Power OK (POK) Modules
5.2.2.2.1.1
POK Programming Model
5.2.2.2.1.1.1
POK Threshold Setting Programming Sequence
5.2.2.2.2
Power on Reset (POR) Module
5.2.2.2.2.1
POR Overview
5.2.2.2.2.2
POR Integration
5.2.2.2.2.3
POR Programming Model
5.2.2.2.3
PoR/Reset Generator (PRG_PP) Modules
5.2.2.2.3.1
PRG_PP Overview
5.2.2.2.3.2
PRG_PP Integration
5.2.2.2.3.3
PRG_PP Programming Model
5.2.2.2.4
Power Glitch Detect (PGD) Modules
5.2.2.2.5
Voltage and Thermal Manager (VTM)
5.2.2.2.5.1
VTM Overview
5.2.2.2.5.1.1
VTM Features
5.2.2.2.5.1.2
VTM Not Supported Features
5.2.2.2.5.2
VTM Integration
5.2.2.2.5.3
VTM Functional Description
5.2.2.2.5.3.1
VTM Temperature Status and Thermal Management
5.2.2.2.5.3.1.1
10-bit Temperature Values Versus Temperature
5.2.2.2.5.3.2
VTM Temperature Driven Alerts and Interrupts
5.2.2.2.5.3.3
VTM VID Voltage Domains
5.2.2.2.5.3.4
VTM Clocking
5.2.2.2.5.3.5
VTM Retention Interface
5.2.2.2.5.3.6
VTM ECC Aggregator
5.2.2.2.5.3.7
VTM Programming Model
5.2.2.2.5.3.7.1
VTM Maximum Temperature Outrange Alert
5.2.2.2.5.3.7.2
Temperature Monitor during Low Power Modes
5.2.2.2.5.3.7.3
Sensors Programming Sequences
5.2.2.2.5.3.8
AVS-Class0
5.2.2.2.6
Distributed Power Clock and Reset Controller (DPCR)
5.2.2.3
Power Control Modules
5.2.2.3.1
Power Sleep Controller and Local Power Sleep Controllers
5.2.2.3.1.1
PSC Terminology
5.2.2.3.1.2
PSC Features
5.2.2.3.1.3
PSC: Device Power-Management Layout
5.2.2.3.1.3.1
WKUP_PSC0 Device-Specific Information
5.2.2.3.1.3.2
PSC0 Device-Specific Information
5.2.2.3.1.3.3
LPSC Dependences Overview
5.2.2.3.1.4
PSC: Power Domain and Module States
5.2.2.3.1.4.1
Power Domain States
5.2.2.3.1.4.2
Module States
5.2.2.3.1.4.3
Local Reset
5.2.2.3.1.5
PSC: Executing State Transitions
5.2.2.3.1.5.1
Power Domain State Transitions
5.2.2.3.1.5.2
Module State Transitions
5.2.2.3.1.5.3
Concurrent Power Domain/Module State Transitions
5.2.2.3.1.5.4
Recommendations for Power Domain/Module Sequencing
5.2.2.3.1.6
PSC: Emulation Support in the PSC
5.2.2.3.1.7
PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
5.2.2.3.1.7.1
ARMi_COREn Power State Transition
5.2.2.3.1.7.2
A72SS Power State Transition
5.2.2.3.1.7.3
GIC0 Sequencing to Support A72SS Power Management
5.2.2.3.1.7.4
MSMC0 Clkstop/Powerdown/Disconnect Sequencing
5.2.2.3.1.7.5
MCU Cortex-R5F Power Modes
5.2.2.3.2
Integrated Power Management (DMSC)
5.2.2.3.2.1
DMSC Power Management Overview
5.2.2.3.2.1.1
DMSC Power Management Features
5.2.3
Device Power States
5.2.3.1
Overview of Device Low-Power Modes
5.2.3.2
Voltage Domains
5.2.3.3
Power Domains
5.2.3.4
Clock Sources States
5.2.3.5
Wake-up Sources
5.2.3.6
Device Power States and Transitions
5.2.3.6.1
LPM Entry Sequences
5.2.3.6.2
LPM Exit Sequences
5.2.3.6.3
IO Retention
5.2.3.6.4
DDRSS Self-Refresh
5.2.4
Dynamic Power Management
5.2.4.1
AVS Support
5.2.4.2
Dynamic Frequency Scaling (DFS) Operations
5.2.5
Thermal Management
5.2.6
Registers
5.2.6.1
WKUP_VTM0 Registers
5.2.6.2
PSC Registers
5.3
Reset
5.3.1
Reset Overview
5.3.2
Reset Sources
5.3.3
Reset Status
5.3.4
Reset Control
5.3.5
BOOTMODE Pins
5.3.6
Reset Sequences
5.3.6.1
MCU_PORz Overview
5.3.6.2
MCU_PORz Sequence
5.3.6.3
MCU_RESETz Sequence
5.3.6.4
PORz Sequence
5.3.6.5
RESET_REQz Sequence
5.3.7
PLL Behavior on Reset
5.4
Clocking
5.4.1
Overview
5.4.2
Clock Inputs
5.4.2.1
Overview
5.4.2.2
Mapping of Clock Inputs
5.4.3
Clock Outputs
5.4.3.1
Observation Clock Pins
5.4.3.1.1
MCU_OBSCLK0 Pin
5.4.3.1.2
424
5.4.3.1.3
OBSCLK0, OBSCLK1, and OBSCLK2 Pins
5.4.3.2
System Clock Pins
5.4.3.2.1
MCU_SYSCLKOUT0
5.4.3.2.2
SYSCLKOUT0
5.4.4
Device Oscillators
5.4.4.1
Device Oscillators Integration
5.4.4.1.1
Oscillators with External Crystal
5.4.4.1.2
Internal RC Oscillator
5.4.4.2
Oscillator Clock Loss Detection
5.4.5
PLLs
5.4.5.1
WKUP and MCU Domains PLL Overview
5.4.5.2
MAIN Domain PLLs Overview
5.4.5.3
PLL Reference Clocks
5.4.5.3.1
PLLs in MCU Domain
5.4.5.3.2
PLLs in MAIN Domain
5.4.5.4
Generic PLL Overview
5.4.5.4.1
PLLs Output Clocks Parameters
5.4.5.4.1.1
PLLs Input Clocks
5.4.5.4.1.2
PLL Output Clocks
5.4.5.4.1.2.1
PLLTS16FFCLAFRAC2 Type Output Clocks
5.4.5.4.1.2.2
PLLTS16FFCLAFRACF Type Output Clocks
5.4.5.4.1.2.3
PLL Lock
5.4.5.4.1.2.4
HSDIVIDER
5.4.5.4.1.2.5
ICG Module
5.4.5.4.1.2.6
PLL Power Down
5.4.5.4.1.2.7
PLL Calibration
5.4.5.4.2
PLL Spread Spectrum Modulation Module
5.4.5.4.2.1
Definition of SSMOD
5.4.5.4.2.2
SSMOD Configuration
5.4.5.5
PLLs Device-Specific Information
5.4.5.5.1
SSMOD Related Bitfields Table
5.4.5.5.2
Clock Synthesis Inputs to the PLLs
5.4.5.5.3
Clock Output Parameter
5.4.5.5.4
Calibration Related Bitfields
5.4.5.6
PLL and PLL Controller Connection
5.4.5.7
PLL, PLLCTRL, and HSDIV Controllers Programming Guide
5.4.5.7.1
PLL Initialization
5.4.5.7.1.1
Kick Protection Mechanism
5.4.5.7.1.2
PLL Initialization to PLL Mode
5.4.5.7.1.3
PLL Programming Requirements
5.4.5.7.2
HSDIV PLL Programming
5.4.5.7.3
PLL Controllers Programming - Dividers PLLDIVn and GO Operation
5.4.5.7.3.1
GO Operation
5.4.5.7.3.2
Software Steps to Modify PLLDIV Ratios
5.4.5.7.4
Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
5.4.6
Registers
5.4.6.1
MCU_PLL0_CFG Registers
5.4.6.2
PLL0_CFG Registers
5.4.6.3
PLLCTRL0 Registers
6
Processors and Accelerators
6.1
Compute Cluster
6.1.1
Compute Cluster Overview
6.1.2
Compute Cluster Functional Description
6.1.2.1
Compute Cluster Memory Regions
6.1.2.2
Compute Cluster Firewalls
6.1.2.3
Compute Cluster ECC Aggregators
6.1.3
Compute Cluster Registers
6.2
Dual-A72 MPU Subsystem
6.2.1
A72SS Overview
6.2.1.1
A72SS Introduction
6.2.1.2
A72SS Features
6.2.2
A72SS Integration
6.2.3
A72SS Functional Description
6.2.3.1
A72SS Block Diagram
6.2.3.2
A72SS A72 Cluster
6.2.3.3
A72SS Interfaces and Async Bridges
6.2.3.4
A72SS Interrupts
6.2.3.4.1
A72SS Interrupt Inputs
6.2.3.4.2
A72SS Interrupt Outputs
6.2.3.5
A72SS Power Management, Clocking and Reset
6.2.3.5.1
A72SS Power Management
6.2.3.5.2
A72SS Clocking
6.2.3.6
A72SS Debug Support
6.2.3.7
A72SS Timestamps
6.2.3.8
A72SS Watchdog
6.2.3.9
A72SS Internal Diagnostics
6.2.3.9.1
A72SS ECC Aggregators During Low Power States
6.2.3.9.2
A72SS CBASS Diagnostics
6.2.3.9.3
A72SS SRAM Diagnostics
6.2.3.9.4
A72SS SRAM ECC Aggregator Configurations
6.2.3.10
A72SS Cache Pre-Warming
6.2.3.11
A72SS Boot
6.2.3.12
A72SS IPC with Other CPUs
6.2.4
A72SS Registers
6.2.4.1
Arm A72 Cluster Registers
6.2.4.2
A72SS ECC Aggregator Registers
6.2.4.2.1
A72SS CLUSTER ECC Registers
6.2.4.2.2
A72SS CORE0 ECC Registers
6.2.4.2.3
A72SS CORE1 ECC Registers
6.3
Dual-R5F MCU Subsystem
6.3.1
R5FSS Overview
6.3.1.1
R5FSS Features
6.3.1.2
R5FSS Not Supported Features
6.3.2
R5FSS Integration
6.3.2.1
R5FSS Integration in MCU Domain
6.3.2.2
R5FSS Integration in MAIN Domain
6.3.3
R5FSS Functional Description
6.3.3.1
R5FSS Block Diagram
6.3.3.2
R5FSS Cortex-R5F Core
6.3.3.2.1
L1 Caches
6.3.3.2.2
Tightly-Coupled Memories (TCMs)
6.3.3.2.3
R5FSS Special Signals
6.3.3.3
R5FSS Interfaces
6.3.3.3.1
R5FSS Master Interfaces
6.3.3.3.2
R5FSS Slave Interfaces
6.3.3.4
R5FSS Power, Clocking and Reset
6.3.3.4.1
R5FSS Power
6.3.3.4.2
R5FSS Clocking
6.3.3.4.2.1
Changing MCU_R5FSS0 CPU Clock Frequency
6.3.3.4.3
R5FSS Reset
6.3.3.5
R5FSS Lockstep Error Detection Logic
6.3.3.5.1
CPU Output Compare Block
6.3.3.5.1.1
Operating Modes
6.3.3.5.1.2
Compare Block Active Mode
6.3.3.5.1.3
Self Test Mode
6.3.3.5.1.4
Compare Match Test
6.3.3.5.1.5
Compare Mismatch Test
6.3.3.5.1.6
Error Forcing Mode
6.3.3.5.1.7
Self Test Error Forcing Mode
6.3.3.5.2
Inactivity Monitor Block
6.3.3.5.2.1
Operating Modes
6.3.3.5.2.2
Compare Block Active Mode
6.3.3.5.2.3
Self Test Mode
6.3.3.5.2.4
Compare Match Test
6.3.3.5.2.5
Compare Mismatch Test
6.3.3.5.2.6
Error Forcing Mode
6.3.3.5.2.7
Self Test Error Forcing Mode
6.3.3.5.3
Polarity Inversion Logic
6.3.3.6
R5FSS Vectored Interrupt Manager (VIM)
6.3.3.6.1
VIM Overview
6.3.3.6.2
VIM Interrupt Inputs
6.3.3.6.3
VIM Interrupt Outputs
6.3.3.6.4
VIM Interrupt Vector Table (VIM RAM)
6.3.3.6.5
VIM Interrupt Prioritization
6.3.3.6.6
VIM ECC Support
6.3.3.6.7
VIM Lockstep Mode
6.3.3.6.8
VIM IDLE State
6.3.3.6.9
VIM Interrupt Handling
6.3.3.6.9.1
Servicing IRQ Through Vector Interface
6.3.3.6.9.2
Servicing IRQ Through MMR Interface
6.3.3.6.9.3
Servicing IRQ Through MMR Interface (Alternative)
6.3.3.6.9.4
Servicing FIQ
6.3.3.6.9.5
Servicing FIQ (Alternative)
6.3.3.7
R5FSS Region Address Translation (RAT)
6.3.3.7.1
RAT Overview
6.3.3.7.2
RAT Operation
6.3.3.7.3
RAT Error Logging
6.3.3.7.4
RAT Protection
6.3.3.8
R5FSS ECC Support
6.3.3.9
R5FSS Memory View
6.3.3.10
R5FSS Debug and Trace
6.3.3.11
R5FSS Boot Options
6.3.3.12
R5FSS Core Memory ECC Events
6.3.4
R5FSS Registers
6.3.4.1
R5FSS_CCMR5 Registers
6.3.4.2
R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
6.3.4.3
R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
6.3.4.4
R5FSS_VIM Registers
6.3.4.5
R5FSS_RAT Registers
6.3.4.6
R5FSS_EVNT_BUS_VBUSP_MMRS Registers
7
Interprocessor Communication
7.1
Mailbox
7.1.1
Mailbox Overview
7.1.1.1
Mailbox Features
7.1.1.2
Mailbox Parameters
7.1.1.3
Mailbox Not Supported Features
7.1.2
Mailbox Integration
7.1.2.1
System Mailbox Integration
7.1.3
Mailbox Functional Description
7.1.3.1
Mailbox Block Diagram
7.1.3.2
Mailbox Software Reset
7.1.3.3
Mailbox Power Management
7.1.3.4
Mailbox Interrupt Requests
7.1.3.5
Mailbox Assignment
7.1.3.5.1
Description
7.1.3.6
Sending and Receiving Messages
7.1.3.6.1
Description
7.1.3.7
Example of Communication
7.1.4
Mailbox Programming Guide
7.1.4.1
Mailbox Low-level Programming Models
7.1.4.1.1
Global Initialization
7.1.4.1.1.1
Surrounding Modules Global Initialization
7.1.4.1.1.2
Mailbox Global Initialization
7.1.4.1.1.2.1
Main Sequence - Mailbox Global Initialization
7.1.4.1.2
Mailbox Operational Modes Configuration
7.1.4.1.2.1
Mailbox Processing modes
7.1.4.1.2.1.1
Main Sequence - Sending a Message (Polling Method)
7.1.4.1.2.1.2
Main Sequence - Sending a Message (Interrupt Method)
7.1.4.1.2.1.3
Main Sequence - Receiving a Message (Polling Method)
7.1.4.1.2.1.4
Main Sequence - Receiving a Message (Interrupt Method)
7.1.4.1.3
Mailbox Events Servicing
7.1.4.1.3.1
Events Servicing in Sending Mode
7.1.4.1.3.2
Events Servicing in Receiving Mode
7.2
Spinlock
7.2.1
Spinlock Overview
7.2.1.1
Spinlock Not Supported Features
7.2.2
Spinlock Integration
7.2.3
Spinlock Functional Description
7.2.3.1
Spinlock Software Reset
7.2.3.2
Spinlock Power Management
7.2.3.3
About Spinlocks
7.2.3.4
Spinlock Functional Operation
7.2.4
Spinlock Programming Guide
7.2.4.1
Spinlock Low-level Programming Models
7.2.4.1.1
Surrounding Modules Global Initialization
7.2.4.1.2
Basic Spinlock Operations
7.2.4.1.2.1
Spinlocks Clearing After a System Bug Recovery
7.2.4.1.2.2
Take and Release Spinlock
8
Memory Controllers
8.1
Multicore Shared Memory Controller (MSMC)
8.1.1
MSMC Overview
8.1.1.1
MSMC Not Supported Features
8.1.2
MSMC Integration
8.1.2.1
MSMC Integration in MAIN Domain
8.1.2.2
639
8.1.3
MSMC Functional Description
8.1.3.1
MSMC Block Diagram
8.1.3.2
MSMC On-Chip Memory Banking
8.1.3.3
MSMC Snoop Filter and Data Cache
8.1.3.3.1
Way Partitioning
8.1.3.3.2
Cache Size Configuration and Associativity
8.1.3.4
MSMC Access Protection Checks
8.1.3.5
MSMC Null Slave
8.1.3.6
MSMC Resource Arbitration
8.1.3.7
MSMC Error Detection and Correction
8.1.3.7.1
On-chip SRAM and Pipeline Data Protection
8.1.3.7.2
On-chip SRAM L3 Cache Tag and Snoop Filter Protection
8.1.3.7.3
On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
8.1.3.7.4
Background Parity Refresh (Scrubbing)
8.1.3.8
MSMC Interrupts
8.1.3.8.1
Raw Interrupt Registers
8.1.3.8.2
Interrupt Enable Registers
8.1.3.8.3
Triggered and Enabled Interrupts
8.1.3.9
MSMC Memory Regions
8.1.3.10
MSMC Hardware Coherence
8.1.3.10.1
Snoop Filter Broadcast Mode
8.1.3.11
MSMC Quality-of-Service
8.1.3.12
MSMC Memory Regions Protection
8.1.3.13
MSMC Cache Tag View
8.1.4
MSMC Registers
8.2
DDR Subsystem (DDRSS)
8.2.1
DDRSS Overview
8.2.1.1
DDRSS Not Supported Features
8.2.2
DDRSS Environment
8.2.3
DDRSS Integration
8.2.3.1
DDRSS Integration in MAIN Domain
8.2.4
DDRSS Functional Description
8.2.4.1
DDRSS MSMC2DDR Bridge
8.2.4.1.1
VBUSM.C Threads
8.2.4.1.2
Class of Service (CoS)
8.2.4.1.3
AXI Write Data All-Strobes
8.2.4.1.4
Inline ECC for SDRAM Data
8.2.4.1.4.1
ECC Cache
8.2.4.1.4.2
ECC Statistics
8.2.4.1.5
Opcode Checking
8.2.4.1.6
Address Alias Prevention
8.2.4.1.7
Data Error Detection and Correction
8.2.4.1.8
AXI Bus Timeout
8.2.4.2
DDRSS Interrupts
8.2.4.3
DDRSS Memory Regions
8.2.4.4
DDRSS ECC Support
8.2.4.5
DDRSS Dynamic Frequency Change Interface
8.2.4.6
DDR Controller Functional Description
8.2.4.6.1
DDR PHY Interface (DFI)
8.2.4.6.2
Command Queue
8.2.4.6.2.1
Placement Logic
8.2.4.6.2.2
Command Selection Logic
8.2.4.6.3
Low Power Control
8.2.4.6.4
Transaction Processing
8.2.4.6.5
BIST Engine
8.2.4.6.6
ECC Engine
8.2.4.6.7
Address Mapping
8.2.4.6.8
Paging Policy
8.2.4.6.9
DDR Controller Initialization
8.2.4.6.10
Programming LPDDR4 Memories
8.2.4.6.10.1
Frequency Set Point (FSP)
8.2.4.6.10.1.1
FSP Mode Register Programming During Initialization
8.2.4.6.10.1.2
FSP Mode Register Programming During Normal Operation
8.2.4.6.10.1.3
FSP Mode Register Programming During Dynamic Frequency Scaling
8.2.4.6.10.2
Data Bus Inversion (DBI)
8.2.4.6.10.3
On-Die Termination
8.2.4.6.10.3.1
LPDDR4 DQ ODT
8.2.4.6.10.3.2
LPDDR4 CA ODT
8.2.4.6.10.4
Byte Lane Swapping
8.2.4.6.10.5
DQS Interval Oscillator
8.2.4.6.10.5.1
Oscillator State Machine
8.2.4.6.10.6
Per-Bank Refresh (PBR)
8.2.4.6.10.6.1
Normal Operation
8.2.4.6.10.6.2
Continuous Refresh Request Mode
8.2.4.7
DDR PHY Functional Description
8.2.4.7.1
Data Slice
8.2.4.7.2
Address Slice
8.2.4.7.2.1
Address Swapping
8.2.4.7.3
Address/Control Slice
8.2.4.7.4
Clock Slice
8.2.4.7.5
DDR PHY Initialization
8.2.4.7.6
DDR PHY Dynamic Frequency Scaling (DFS)
8.2.4.7.7
Chip Select and Frequency Based Register Settings
8.2.4.7.8
Low-Power Modes
8.2.4.7.9
Training Support
8.2.4.7.9.1
Write Leveling
8.2.4.7.9.2
Read Gate Training
8.2.4.7.9.3
Read Data Eye Training
8.2.4.7.9.4
Write DQ Training
8.2.4.7.9.5
CA Training
8.2.4.7.9.6
CS Training
8.2.4.7.10
Data Bus Inversion (DBI)
8.2.4.7.11
I/O Pad Calibration
8.2.4.7.12
DQS Error
8.2.4.8
PI Functional Description
8.2.4.8.1
PI Initialization
8.2.5
DDRSS Registers
8.2.5.1
DDR Subsystem Registers
8.2.5.2
DDR Controller Registers
8.2.5.3
PI Registers
8.2.5.4
DDR PHY Registers
8.2.5.5
DDRSS0_ECC_AGGR_CTL Registers
8.2.5.6
DDRSS0_ECC_AGGR_VBUS Registers
8.2.5.7
DDRSS0_ECC_AGGR_CFG Registers
8.3
Peripheral Virtualization Unit (PVU)
8.3.1
PVU Overview
8.3.1.1
PVU Features
8.3.1.2
PVU Parameters
8.3.1.3
PVU Not Supported Features
8.3.2
PVU Integration
8.3.3
PVU Functional Description
8.3.3.1
Functional Operation Overview
8.3.3.2
PVU Channels
8.3.3.3
TLB
8.3.3.4
TLB Entry
8.3.3.5
TLB Selection
8.3.3.6
DMA Classes
8.3.3.7
General virtIDs
8.3.3.8
TLB Lookup
8.3.3.9
TLB Miss
8.3.3.10
Multiple Matching Entries
8.3.3.11
TLB Disable
8.3.3.12
TLB Chaining
8.3.3.13
TLB Permissions
8.3.3.14
Translation
8.3.3.15
Memory Attributes
8.3.3.16
Faulted Transactions
8.3.3.17
Non-Virtual Transactions
8.3.3.18
Allowed virtIDs
8.3.3.19
Software Control
8.3.3.20
Fault Logging
8.3.3.21
Alignment Restrictions
8.3.4
PVU Registers
8.3.4.1
NAVSS_PVU_CFG Registers
8.3.4.2
NAVSS0_PVU_CFG_TLBIF Registers
8.4
Region-based Address Translation (RAT) Module
8.4.1
RAT Functional Description
8.4.1.1
RAT Availability
8.4.1.2
RAT Operation
8.4.1.3
RAT Error Logging
8.4.2
RAT Registers
9
Interrupts
9.1
Interrupt Architecture
9.2
Interrupt Controllers
9.2.1
Generic Interrupt Controller (GIC)
9.2.1.1
GIC Overview
9.2.1.1.1
GIC Features
9.2.1.1.2
GIC Not Supported Features
9.2.1.2
GIC Integration
9.2.1.3
GIC Functional Description
9.2.1.3.1
GIC Block Diagram
9.2.1.3.2
Arm GIC-500
9.2.1.3.3
GIC Interrupt Types
9.2.1.3.4
GIC Interfaces
9.2.1.3.5
GIC Interrupt Outputs
9.2.1.3.6
GIC ECC Support
9.2.1.3.7
GIC AXI2VBUSM and VBUSM2AXI Bridges
9.2.1.4
GIC Registers
9.2.1.4.1
Arm GIC-500 Registers
9.2.1.4.2
GIC_ECC_AGGR Registers
9.2.2
Other Interrupt Controllers
9.3
Interrupt Routers
9.3.1
INTRTR Overview
9.3.2
INTRTR Integration
9.3.2.1
WKUP_GPIOMUX_INTRTR0 Integration
9.3.2.2
GPIOMUX_INTRTR0 Integration
9.3.2.3
MAIN2MCU_LVL_INTRTR0 Integration
9.3.2.4
MAIN2MCU_PLS_INTRTR0 Integration
9.3.3
INTRTR Registers
9.3.3.1
WKUP_GPIOMUX_INTRTR0 Registers
9.3.3.2
GPIOMUX_INTRTR0 Registers
9.3.3.3
MAIN2MCU_LVL_INTRTR0 Registers
9.3.3.4
MAIN2MCU_PLS_INTRTR0 Registers
9.4
Interrupt Sources
9.4.1
WKUP Domain Interrupt Maps
9.4.1.1
WKUP_DMSC0 Interrupt Map
9.4.1.2
WKUP_GPIOMUX_INTRTR0 Interrupt Map
9.4.1.3
WKUP_GPIO0_VIRT Interrupt Map
9.4.1.4
WKUP_ESM0 Interrupt Map
9.4.2
MCU Domain Interrupt Maps
9.4.2.1
MCU_R5FSS0_CORE0 Interrupt Map
9.4.2.2
MCU_R5FSS0_CORE1 Interrupt Map
9.4.2.3
MCU_ESM0 Interrupt Map
9.4.3
MAIN Domain Interrupt Maps
9.4.3.1
COMPUTE_CLUSTER0 Interrupt Map
9.4.3.1.1
GIC500 PPI Interrupt Map
9.4.3.1.2
GIC500 SPI Interrupt Map
9.4.3.1.3
SoC Event Output Interrupt Map
9.4.3.2
R5FSS0_CORE0 Interrupt Map
9.4.3.3
R5FSS0_CORE1 Interrupt Map
9.4.3.4
MAIN2MCU_LVL_INTRTR0 Interrupt Map
9.4.3.5
MAIN2MCU_PLS_INTRTR0 Interrupt Map
9.4.3.6
GPIOMUX_INTRTR0 Interrupt Map
9.4.3.7
GPIO0_VIRT Interrupt Map
9.4.3.8
ESM0 Interrupt Map
10
Data Movement Architecture (DMA)
10.1
DMA Architecture
10.1.1
Overview
10.1.1.1
Navigator Subsystem
10.1.1.2
Ring Accelerator (RA)
10.1.1.3
Proxy
10.1.1.4
Secure Proxy
10.1.1.5
Interrupt Aggregator (INTA)
10.1.1.6
Interrupt Router (IR)
10.1.1.7
Unified DMA – Third Party Channel Controller (UDMA-C)
10.1.1.8
Unified Transfer Controller (UTC)
10.1.1.9
Data Routing Unit (DRU)
10.1.1.10
Unified DMA – Peripheral Root Complex (UDMA-P)
10.1.1.10.1
Channel Classes
10.1.1.11
Peripheral DMA (PDMA)
10.1.1.12
Embedded DMA
10.1.1.13
Definition of Terms
10.1.2
UDMA Hardware/Software Interface
10.1.2.1
Data Buffers
10.1.2.2
Descriptors
10.1.2.2.1
Host Packet Descriptor
10.1.2.2.2
Host Buffer Descriptor
10.1.2.2.3
Monolithic Packet Descriptor
10.1.2.2.4
Transfer Request Descriptor
10.1.2.3
Transfer Request Record
10.1.2.3.1
Overview
10.1.2.3.2
Addressing Algorithm
10.1.2.3.2.1
Linear Addressing (Forward)
10.1.2.3.3
Transfer Request Formats
10.1.2.3.4
Flags Field Definition
10.1.2.3.4.1
Type: TR Type Field
10.1.2.3.4.2
STATIC: Static Field Definition
10.1.2.3.4.3
EVENT_SIZE: Event Generation Definition
10.1.2.3.4.4
TRIGGER INFO: TR Triggers
10.1.2.3.4.5
TRIGGERX_TYPE: Trigger Type
10.1.2.3.4.6
TRIGGERX: Trigger Selection
10.1.2.3.4.7
CMD ID: Command ID Field Definition
10.1.2.3.4.8
Configuration Specific Flags Definition
10.1.2.3.5
TR Address and Size Attributes
10.1.2.3.5.1
ICNT0
10.1.2.3.5.2
ICNT1
10.1.2.3.5.3
ADDR
10.1.2.3.5.4
DIM1
10.1.2.3.5.5
ICNT2
10.1.2.3.5.6
ICNT3
10.1.2.3.5.7
DIM2
10.1.2.3.5.8
DIM3
10.1.2.3.5.9
DDIM1
10.1.2.3.5.10
DADDR
10.1.2.3.5.11
DDIM2
10.1.2.3.5.12
DDIM3
10.1.2.3.5.13
DICNT0
10.1.2.3.5.14
DICNT1
10.1.2.3.5.15
DICNT2
10.1.2.3.5.16
DICNT3
10.1.2.3.6
FMTFLAGS
10.1.2.3.6.1
AMODE: Addressing Mode Definition
10.1.2.3.6.1.1
Linear Addressing
10.1.2.3.6.1.2
Circular Addressing
10.1.2.3.6.2
DIR: Addressing Mode Direction Definition
10.1.2.3.6.3
ELTYPE: Element Type Definition
10.1.2.3.6.4
DFMT: Data Formatting Algorithm Definition
10.1.2.3.6.5
SECTR: Secondary Transfer Request Definition
10.1.2.3.6.5.1
Secondary TR Formats
10.1.2.3.6.5.2
Secondary TR FLAGS
10.1.2.3.6.5.2.1
SEC_TR_TYPE: Secondary TR Type Field
10.1.2.3.6.5.2.2
Multiple Buffer Interleave
10.1.2.3.6.6
AMODE SPECIFIC: Addressing Mode Field
10.1.2.3.6.6.1
Circular Address Mode Specific Flags
10.1.2.3.6.6.1.1
CBK0 and CBK1: Circular Block Size Selection
10.1.2.3.6.6.1.2
Amx: Addressing Mode Selection
10.1.2.3.6.7
Cache Flags
10.1.2.4
Transfer Response Record
10.1.2.4.1
STATUS Field Definition
10.1.2.4.1.1
STATUS_TYPE Definition
10.1.2.4.1.1.1
Transfer Error
10.1.2.4.1.1.2
Aborted Error
10.1.2.4.1.1.3
Submission Error
10.1.2.4.1.1.4
Unsupported Feature
10.1.2.4.1.1.5
Transfer Exception
10.1.2.4.1.1.6
Teardown Flush
10.1.2.5
Queues
10.1.2.5.1
Queue Types
10.1.2.5.1.1
Transmit Queues (Pass By Reference)
10.1.2.5.1.2
Transmit Queues (Pass By Value)
10.1.2.5.1.3
Transmit Completion Queues (Pass By Reference)
10.1.2.5.1.4
Transmit Completion Queues (Pass By Value)
10.1.2.5.1.5
Receive Queues
10.1.2.5.1.6
Free Descriptor Queues
10.1.2.5.1.7
Free Descriptor/Buffer Queues
10.1.2.5.2
Ring Accelerator Queues Implementation
10.1.3
Operational Description
10.1.3.1
Resource Allocation
10.1.3.2
Ring Accelerator Operation
10.1.3.2.1
Queue Initialization
10.1.3.2.2
Queuing packets (Exposed Ring Mode)
10.1.3.2.3
De-queuing packets (Exposed Ring Mode)
10.1.3.2.4
Queuing packets (Queue Mode)
10.1.3.2.5
De-queuing packets (Queue Mode)
10.1.3.3
UDMA Internal Transmit Channel Setup (All Packet Types)
10.1.3.4
UDMA Internal Transmit Channel Teardown (All Packet Types)
10.1.3.5
UDMA External Transmit Channel Setup
10.1.3.6
UDMA Transmit External Channel Teardown
10.1.3.7
UDMA-P Transmit Channel Pause
10.1.3.8
UDMA-P Transmit Operation (Host Packet Type)
10.1.3.9
UDMA-P Transmit Operation (Monolithic Packet)
10.1.3.10
UDMA Transmit Operation (TR Packet)
10.1.3.11
UDMA Transmit Operation (Direct TR)
10.1.3.12
UDMA Transmit Error/Exception Handling
10.1.3.12.1
Null Icnt0 Error
10.1.3.12.2
Unsupported TR Type
10.1.3.12.3
Bus Errors
10.1.3.13
UDMA Receive Channel Setup (All Packet Types)
10.1.3.14
UDMA Receive Channel Teardown
10.1.3.15
UDMA-P Receive Channel Pause
10.1.3.16
UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
10.1.3.17
UDMA-P Receive FlowID Firewall Operation
10.1.3.18
UDMA-P Receive Operation (Host Packet)
10.1.3.19
UDMA-P Receive Operation (Monolithic Packet)
10.1.3.20
UDMA Receive Operation (TR Packet)
10.1.3.21
UDMA Receive Operation (Direct TR)
10.1.3.22
UDMA Receive Error/Exception Handling
10.1.3.22.1
Error Conditions
10.1.3.22.1.1
Bus Errors
10.1.3.22.1.2
Null Icnt0 Error
10.1.3.22.1.3
Unsupported TR Type
10.1.3.22.2
Exception Conditions Exception Conditions
10.1.3.22.2.1
Descriptor Starvation
10.1.3.22.2.2
Protocol Errors
10.1.3.22.2.3
Dropped Packets
10.1.3.22.2.4
Reception of EOL Delimiter
10.1.3.22.2.5
EOP Asserted Prematurely (Short Packet)
10.1.3.22.2.6
EOP Asserted Late (Long Packets)
10.1.3.23
UTC Operation
10.1.3.24
UTC Receive Error/Exception Handling
10.1.3.24.1
Error Handling
10.1.3.24.1.1
Null Icnt0 Error
10.1.3.24.1.2
Unsupported TR Type
10.1.3.24.2
Exception Conditions
10.1.3.24.2.1
Reception of EOL Delimiter
10.1.3.24.2.2
EOP Asserted Prematurely (Short Packet)
10.1.3.24.2.3
EOP Asserted Late (Long Packets)
10.2
Navigator Subsystem (NAVSS)
10.2.1
Main Navigator Subsystem (NAVSS)
10.2.1.1
NAVSS Overview
10.2.1.2
NAVSS Integration
10.2.1.2.1
NAVSS Interrupt Router Configuration
10.2.1.2.2
Global Event Map
10.2.1.2.3
PSI-L System Thread Map (All NAVSS)
10.2.1.2.4
NAVSS VBUSM Route ID Table
10.2.1.3
NAVSS Functional Description
10.2.1.4
NAVSS Interrupt Configuration
10.2.1.4.1
NAVSS Event and Interrupt Flow
10.2.1.4.1.1
NAVSS Interrupts Description
10.2.1.4.1.2
Application Example
10.2.1.5
NAVSS Top-level Registers
10.2.1.5.1
NAVSS0_CFG Registers
10.2.1.5.2
INTR0_INTR_ROUTER_CFG Registers
10.2.1.5.3
VIRTID_CFG_MMRS Registers
10.2.2
MCU Navigator Subsystem (MCU NAVSS)
10.2.2.1
MCU NAVSS Overview
10.2.2.2
MCU NAVSS Integration
10.2.2.2.1
MCU NAVSS Interrupt Router Configuration
10.2.2.2.2
MCU NAVSS UDMASS Interrupt Aggregator Configuration
10.2.2.2.3
MCU NAVSS UDMA Configuration
10.2.2.2.4
MCU NAVSS Ring Accelerator Configuration
10.2.2.2.5
MCU NAVSS Proxy Configuration
10.2.2.2.6
MCU NAVSS Secure Proxy Configuration
10.2.2.2.7
Global Event Map
10.2.2.2.8
PSI-L System Thread Map (All NAVSS)
10.2.2.2.9
MCU NAVSS VBUSM Route ID Table
10.2.2.2.10
1006
10.2.2.3
MCU NAVSS Functional Description
10.2.2.4
MCU NAVSS Top-Level Registers
10.2.2.4.1
MCU_NAVSS0_CFG Registers
10.2.2.4.2
MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
10.2.3
Unified DMA Controller (UDMA)
10.2.3.1
UDMA Overview
10.2.3.1.1
UDMA Features
10.2.3.1.2
UDMA Parameters
10.2.3.2
UDMA Integration
10.2.3.3
UDMA Functional Description
10.2.3.3.1
Block Diagram
10.2.3.3.2
General Functionality
10.2.3.3.2.1
Operational States
10.2.3.3.2.2
Tx Channel Allocation
10.2.3.3.2.3
Rx Channel Allocation
10.2.3.3.2.4
Tx Teardown
10.2.3.3.2.5
Rx Teardown
10.2.3.3.2.6
Tx Clock Stop
10.2.3.3.2.7
Rx Clock Stop
10.2.3.3.2.8
Rx Thread Enables
10.2.3.3.2.9
Events
10.2.3.3.2.9.1
Local Event Inputs
10.2.3.3.2.9.2
Inbound Tx PSI-L Events
10.2.3.3.2.9.3
Outbound Rx PSI-L Events
10.2.3.3.2.10
Emulation Control
10.2.3.3.3
Packet Oriented Transmit Operation
10.2.3.3.3.1
Packet Mode VBUSM Master Interface Command ID Selection
10.2.3.3.4
Packet Oriented Receive Operation
10.2.3.3.4.1
Rx Packet Drop
10.2.3.3.4.2
Rx Starvation and the Starvation Timer
10.2.3.3.5
Third Party Mode Operation
10.2.3.3.5.1
Events and Flow Control
10.2.3.3.5.1.1
Channel Triggering
10.2.3.3.5.1.2
Internal TR Completion Events
10.2.3.3.5.2
Transmit Operation
10.2.3.3.5.2.1
Transfer Request
10.2.3.3.5.2.2
Transfer Response
10.2.3.3.5.2.3
Data Transfer
10.2.3.3.5.2.4
Memory Interface Transactions
10.2.3.3.5.2.5
Error Handling
10.2.3.3.5.3
Receive Operation
10.2.3.3.5.3.1
Transfer Request
10.2.3.3.5.3.2
Transfer Response
10.2.3.3.5.3.3
Error Handling
10.2.3.3.5.4
Data Transfer
10.2.3.3.5.4.1
Memory Interface Transactions
10.2.3.3.5.4.2
Rx Packet Drop
10.2.3.4
UDMA Registers
10.2.3.4.1
UDMASS_UDMAP0_CFG Registers
10.2.3.4.2
UDMASS_UDMAP0_CFG_TCHAN Registers
10.2.3.4.3
UDMASS_UDMAP0_CFG_RCHAN Registers
10.2.3.4.4
UDMASS_UDMAP0_CFG_RFLOW Registers
10.2.3.4.5
UDMASS_UDMAP0_CFG_RCHANRT Registers
10.2.3.4.6
UDMASS_UDMAP0_CFG_TCHANRT Registers
10.2.4
Ring Accelerator (RINGACC)
10.2.4.1
RINGACC Overview
10.2.4.1.1
RINGACC Features
10.2.4.1.2
RINGACC Not Supported Features
10.2.4.1.3
RINGACC Parameters
10.2.4.2
RINGACC Integration
10.2.4.3
RINGACC Functional Description
10.2.4.3.1
Block Diagram
10.2.4.3.1.1
Configuration Registers
10.2.4.3.1.2
Source Command FIFO
10.2.4.3.1.3
Source Write Data FIFO
10.2.4.3.1.4
Source Read Data FIFO
10.2.4.3.1.5
Source Write Status FIFO
10.2.4.3.1.6
Main State Machine
10.2.4.3.1.7
Destination Command FIFO
10.2.4.3.1.8
Destination Write Data FIFO
10.2.4.3.1.9
Destination Read Data FIFO
10.2.4.3.1.10
Destination Write Status FIFO
10.2.4.3.2
RINGACC Functional Operation
10.2.4.3.2.1
Queue Modes
10.2.4.3.2.1.1
Ring Mode
10.2.4.3.2.1.2
Messaging Mode
10.2.4.3.2.1.3
Credentials Mode
10.2.4.3.2.1.4
Queue Manager Mode
10.2.4.3.2.1.5
Peek Support
10.2.4.3.2.1.6
Index Register Operation
10.2.4.3.2.2
VBUSM Slave Ring Operations
10.2.4.3.2.3
VBUSM Master Interface Command ID Selection
10.2.4.3.2.4
Ring Push Operation (VBUSM Write to Source Interface)
10.2.4.3.2.5
Ring Pop Operation (VBUSM Read from Source Interface)
10.2.4.3.2.6
Host Doorbell Access
10.2.4.3.2.7
Queue Push Operation (VBUSM Write to Source Interface)
10.2.4.3.2.8
Queue Pop Operation (VBUSM Read from Source Interface)
10.2.4.3.2.9
Mismatched Element Size Handling
10.2.4.3.3
Events
10.2.4.3.4
Bus Error Handling
10.2.4.3.5
Monitors
10.2.4.3.5.1
Threshold Monitor
10.2.4.3.5.2
Watermark Monitor
10.2.4.3.5.3
Starvation Monitor
10.2.4.3.5.4
Statistics Monitor
10.2.4.3.5.5
Overflow
10.2.4.3.5.6
Ring Update Port
10.2.4.3.5.7
Tracing
10.2.4.4
RINGACC Registers
10.2.4.4.1
NAVSS0_UDMASS_RINGACC0_CFG Registers
10.2.4.4.2
NAVSS0_UDMASS_RINGACC0_GCFG Registers
10.2.4.4.3
NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
10.2.4.4.4
NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
10.2.4.4.5
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
10.2.5
Proxy
10.2.5.1
Proxy Overview
10.2.5.1.1
Proxy Features
10.2.5.1.2
Proxy Parameters
10.2.5.1.3
Proxy Not Supported Features
10.2.5.2
Proxy Integration
10.2.5.3
Proxy Functional Description
10.2.5.3.1
Targets
10.2.5.3.1.1
Ring Accelerator
10.2.5.3.2
Proxy Sizes
10.2.5.3.3
Proxy Interleaving
10.2.5.3.4
Proxy Host States
10.2.5.3.5
Proxy Host Channel Selection
10.2.5.3.6
Proxy Host Access
10.2.5.3.6.1
Proxy Host Writes
10.2.5.3.6.2
Proxy Host Reads
10.2.5.3.7
Permission Inheritance
10.2.5.3.8
Buffer Size
10.2.5.3.9
Error Events
10.2.5.3.10
Debug Reads
10.2.5.4
Proxy Registers
10.2.5.4.1
NAVSS0_PROXY0_CFG_BUF_CFG Registers
10.2.5.4.2
NAVSS0_PROXY0_BUF_CFG Registers
10.2.5.4.3
NAVSS0_PROXY_BUF Registers
10.2.5.4.4
NAVSS0_PROXY_TARGET0_DATA Registers
10.2.6
Secure Proxy
10.2.6.1
Secure Proxy Overview
10.2.6.1.1
Secure Proxy Features
10.2.6.1.2
Secure Proxy Parameters
10.2.6.1.3
Secure Proxy Not Supported Features
10.2.6.2
Secure Proxy Integration
10.2.6.3
Secure Proxy Functional Description
10.2.6.3.1
Targets
10.2.6.3.1.1
Ring Accelerator
10.2.6.3.2
Buffers
10.2.6.3.2.1
Proxy Credits
10.2.6.3.2.2
Proxy Private Word
10.2.6.3.2.3
Completion Byte
10.2.6.3.3
Proxy Thread Sizes
10.2.6.3.4
Proxy Thread Interleaving
10.2.6.3.5
Proxy States
10.2.6.3.6
Proxy Host Access
10.2.6.3.6.1
Proxy Host Writes
10.2.6.3.6.2
Proxy Host Reads
10.2.6.3.6.3
Buffer Accesses
10.2.6.3.6.4
Target Access
10.2.6.3.6.5
Error State
10.2.6.3.7
Permission Inheritance
10.2.6.3.8
Resource Association
10.2.6.3.9
Direction
10.2.6.3.10
Threshold Events
10.2.6.3.11
Error Events
10.2.6.3.12
Bus Errors and Credits
10.2.6.3.13
Debug
10.2.6.4
Secure Proxy Registers
10.2.6.4.1
NAVSS0_SEC_PROXY0_CFG_MMRS Registers
10.2.6.4.2
NAVSS0_SEC_PROXY0_CFG_RT Registers
10.2.6.4.3
NAVSS0_SEC_PROXY0_CFG_SCFG Registers
10.2.6.4.4
NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
10.2.7
Interrupt Aggregator (INTR_AGGR)
10.2.7.1
INTR_AGGR Overview
10.2.7.1.1
INTR_AGGR Features
10.2.7.1.2
INTR_AGGR Parameters
10.2.7.2
INTR_AGGR Integration
10.2.7.3
INTR_AGGR Functional Description
10.2.7.3.1
Submodule Descriptions
10.2.7.3.1.1
Status/Mask Registers
10.2.7.3.1.2
Interrupt Mapping Block
10.2.7.3.1.3
Global Event Input (GEVI) Counters
10.2.7.3.1.4
Local Event Input (LEVI) to Global Event Conversion
10.2.7.3.1.5
Global Event Multicast
10.2.7.3.2
General Functionality
10.2.7.3.2.1
Event to Interrupt Bit Steering
10.2.7.3.2.2
Interrupt Status
10.2.7.3.2.3
Interrupt Masked Status
10.2.7.3.2.4
Enabling/Disabling Individual Interrupt Source Bits
10.2.7.3.2.5
Interrupt Output Generation
10.2.7.3.2.6
Global Event Counting
10.2.7.3.2.7
Local Event to Global Event Conversion
10.2.7.3.2.8
Global Event Multicast
10.2.7.4
INTR_AGGR Registers
10.2.7.4.1
MODSS_INTA_CFG Registers
10.2.7.4.2
MODSS_INTA_CFG_IMAP Registers
10.2.7.4.3
MODSS_INTA_CFG_INTR Registers
10.2.7.4.4
UDMASS_INTA0_CFG Registers
10.2.7.4.5
UDMASS_INTA0_CFG_INTR Registers
10.2.7.4.6
UDMASS_INTA0_CFG_IMAP Registers
10.2.7.4.7
UDMASS_INTA0_CFG_L2G Registers
10.2.7.4.8
UDMASS_INTA0_CFG_MCAST Registers
10.2.7.4.9
UDMASS_INTA0_CFG_GCNTCFG Registers
10.2.7.4.10
UDMASS_INTA0_CFG_GCNTRTI Registers
10.2.8
Packet Streaming Interface Link (PSI-L)
10.2.8.1
PSI-L Overview
10.2.8.2
PSI-L Functional Description
10.2.8.2.1
PSI-L Introduction
10.2.8.2.2
PSI-L Operation
10.2.8.2.2.1
Event Transport
10.2.8.2.2.2
Threads
10.2.8.2.2.3
Arbitration Protocol
10.2.8.2.2.4
Thread Configuration
10.2.8.2.2.4.1
Thread Pairing
10.2.8.2.2.4.1.1
Configuration Transaction Pairing
10.2.8.2.2.4.2
Configuration Registers Region
10.2.8.3
PSI-L Configuration Registers
10.2.8.4
PSI-L CFG_PROXY Registers
10.2.9
PSIL Subsystem (PSILSS)
10.2.9.1
PSILSS Overview
10.2.9.1.1
PSILSS Features
10.2.9.2
PSILSS Functional Description
10.2.9.2.1
PSILSS Basic Operation
10.2.9.2.2
PSILSS Event Routing
10.2.9.2.3
PSILSS Link Down Detection
10.2.9.2.4
PSILSS Configuration
10.2.9.3
PSILSS Registers
10.2.9.3.1
PDMA_USART_PSILSS0 Registers
10.2.9.3.2
PDMA_SPI_PSILSS0 Registers
10.2.10
NAVSS North Bridge (NB)
10.2.10.1
NB Overview
10.2.10.1.1
Features Supported
10.2.10.1.2
NB Parameters
10.2.10.1.2.1
Compliance to Standards
10.2.10.1.2.2
Features Not Supported
10.2.10.2
NB Functional Description
10.2.10.2.1
VBUSM Slave Interfaces
10.2.10.2.2
VBUSM Master Interface
10.2.10.2.3
VBUSM.C Interfaces
10.2.10.2.3.1
Multi-Threading
10.2.10.2.3.2
Write Command Crediting
10.2.10.2.3.3
Early Credit Response
10.2.10.2.3.4
Priority Escalation
10.2.10.2.4
Source M2M Bridges
10.2.10.2.5
Destination M2M Bridge
10.2.10.2.6
M2C Bridge
10.2.10.2.7
Memory Attribute Tables
10.2.10.2.8
Outstanding Read Data Limiter
10.2.10.2.9
Ordering
10.2.10.2.10
Quality of Service
10.2.10.2.11
IDLE Behavior
10.2.10.2.12
Clock Power Management
10.2.10.3
NB Registers
10.2.10.3.1
NAVSS0_NBSS_CFG_REGS0_MMRS Registers
10.2.10.3.2
NAVSS0_NBSS_NB_CFG_MMRS Registers
10.3
Peripheral DMA (PDMA)
10.3.1
PDMA Controller
10.3.1.1
PDMA Overview
10.3.1.1.1
PDMA Features
10.3.1.1.1.1
MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
10.3.1.1.1.2
MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
10.3.1.1.1.3
MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
10.3.1.1.1.4
MCU_PDMA3 (MCU_PDMA_ADC) Features
10.3.1.1.1.5
PDMA2 (PDMA_DEBUG_CCMCU) Features
10.3.1.1.1.6
PDMA5 (PDMA_MCAN) Features
10.3.1.1.1.7
PDMA6 (PDMA_MCASP_G0) Features
10.3.1.1.1.8
PDMA9 (PDMA_SPI_G0) Features
10.3.1.1.1.9
PDMA10 (PDMA_SPI_G1) Features
10.3.1.1.1.10
PDMA13 (PDMA_USART_G0) Features
10.3.1.1.1.11
PDMA14 (PDMA_USART_G1) Features
10.3.1.1.1.12
PDMA15 (PDMA_USART_G2) Features
10.3.1.2
PDMA Integration
10.3.1.2.1
PDMA Integration in MCU Domain
10.3.1.2.2
PDMA Integration in MAIN Domain
10.3.1.3
PDMA Functional Description
10.3.1.3.1
PDMA Functional Blocks
10.3.1.3.1.1
Scheduler
10.3.1.3.1.2
Tx Per-Channel Buffers (TCP FIFO)
10.3.1.3.1.3
Tx DMA Unit (Tx Engine)
10.3.1.3.1.4
Rx Per-Channel Buffers (RCP FIFO)
10.3.1.3.1.5
Rx DMA Unit (Rx Engine)
10.3.1.3.2
PDMA General Functionality
10.3.1.3.2.1
Operational States
10.3.1.3.2.2
Clock Stop
10.3.1.3.2.3
Emulation Control
10.3.1.3.3
PDMA Events and Flow Control
10.3.1.3.3.1
Channel Types
10.3.1.3.3.1.1
X-Y FIFO Mode
10.3.1.3.3.1.2
MCAN Mode
10.3.1.3.3.1.3
AASRC Mode
10.3.1.3.3.1.4
1288
10.3.1.3.3.2
Channel Triggering
10.3.1.3.3.3
Completion Events
10.3.1.3.4
PDMA Transmit Operation
10.3.1.3.4.1
Destination (Tx) Channel Allocation
10.3.1.3.4.2
Destination (Tx) Channel Out-of-Band Signals
10.3.1.3.4.3
Destination Channel Initialization
10.3.1.3.4.3.1
PSI-L Destination Thread Pairing
10.3.1.3.4.3.2
Static Transfer Request Setup
10.3.1.3.4.3.3
1297
10.3.1.3.4.3.4
PSI-L Destination Thread Enables
10.3.1.3.4.4
Data Transfer
10.3.1.3.4.4.1
X-Y FIFO Mode Channel
10.3.1.3.4.4.1.1
X-Y FIFO Burst Mode
10.3.1.3.4.4.2
MCAN Mode Channel
10.3.1.3.4.4.2.1
MCAN Burst Mode
10.3.1.3.4.4.3
AASRC Mode Channel
10.3.1.3.4.5
Tx Pause
10.3.1.3.4.6
Tx Teardown
10.3.1.3.4.7
Tx Channel Reset
10.3.1.3.4.8
Tx Debug/State Registers
10.3.1.3.5
PDMA Receive Operation
10.3.1.3.5.1
Source (Rx) Channel Allocation
10.3.1.3.5.2
Source Channel Initialization
10.3.1.3.5.2.1
PSI-L Source Thread Pairing
10.3.1.3.5.2.2
Static Transfer Request Setup
10.3.1.3.5.2.3
PSI-L Source Thread Enables
10.3.1.3.5.3
Data Transfer
10.3.1.3.5.3.1
X-Y FIFO Mode Channel
10.3.1.3.5.3.2
MCAN Mode Channel
10.3.1.3.5.3.2.1
MCAN Burst Mode
10.3.1.3.5.3.3
AASRC Mode Channel
10.3.1.3.5.4
Rx Pause
10.3.1.3.5.5
Rx Teardown
10.3.1.3.5.6
Rx Channel Reset
10.3.1.3.5.7
Rx Debug/State Register
10.3.1.3.6
PDMA ECC Support
10.3.1.4
PDMA Registers
10.3.1.4.1
PDMA5 ECC Registers
10.3.1.4.2
PDMA9 ECC Registers
10.3.1.4.3
PDMA10 ECC Registers
10.3.1.4.4
PDMA PSI-L TX Configuration Registers
10.3.1.4.5
PDMA PSI-L RX Configuration Registers
10.3.2
PDMA Sources
10.3.2.1
MCU Domain PDMA Event Maps
10.3.2.1.1
MCU_PDMA_MISC_G0 Event Map
10.3.2.1.2
MCU_PDMA_MISC_G1 Event Map
10.3.2.1.3
MCU_PDMA_MISC_G2 Event Map
10.3.2.1.4
MCU_PDMA_ADC Event Map
10.3.2.2
MAIN Domain PDMA Event Maps
10.3.2.2.1
PDMA_DEBUG_CCMCU Event Map
10.3.2.2.2
PDMA_MCAN Event Map
10.3.2.2.3
PDMA_MCASP_G0 Event Map
10.3.2.2.4
PDMA_SPI_G0 Event Map
10.3.2.2.5
PDMA_SPI_G1 Event Map
10.3.2.2.6
PDMA_USART_G0 Event Map
10.3.2.2.7
PDMA_USART_G1 Event Map
10.3.2.2.8
PDMA_USART_G2 Event Map
11
Time Sync
11.1
Time Sync Module (CPTS)
11.1.1
CPTS Overview
11.1.1.1
CPTS Features
11.1.1.2
CPTS Not Supported Features
11.1.2
CPTS Integration
11.1.3
CPTS Functional Description
11.1.3.1
CPTS Architecture
11.1.3.2
CPTS Initialization
11.1.3.3
32-bit Time Stamp Value
11.1.3.4
64-bit Time Stamp Value
11.1.3.4.1
64-Bit Timestamp Nudge
11.1.3.4.2
64-bit Timestamp PPM
11.1.3.5
Event FIFO
11.1.3.6
Timestamp Compare Output
11.1.3.6.1
Non-Toggle Mode
11.1.3.6.2
Toggle Mode
11.1.3.7
Timestamp Sync Output
11.1.3.8
Timestamp GENF Output
11.1.3.8.1
GENFn Nudge
11.1.3.8.2
GENFn PPM
11.1.3.9
Time Sync Events
11.1.3.9.1
Time Stamp Push Event
11.1.3.9.2
Time Stamp Counter Rollover Event (32-bit mode only)
11.1.3.9.3
Time Stamp Counter Half-rollover Event (32-bit mode only)
11.1.3.9.4
Hardware Time Stamp Push Event
11.1.3.10
Timestamp Compare Event
11.1.3.11
CPTS Interrupt Handling
11.1.4
CPTS Registers
11.2
Timer Manager
11.2.1
Timer Manager Overview
11.2.1.1
Timer Manager Features
11.2.1.2
Timer Manager Not Supported Features
11.2.2
Timer Manager Integration
11.2.3
Timer Manager Functional Description
11.2.3.1
Timer Manager Function Overview
11.2.3.2
Timer Counter
11.2.3.2.1
Timer Counter Rollover
11.2.3.3
Timer Control Module (FSM)
11.2.3.4
Timer Reprogramming
11.2.3.4.1
Periodic Hardware Timers
11.2.3.5
Event FIFO
11.2.3.6
Output Event Lookup (OES RAM)
11.2.4
Timer Manager Programming Guide
11.2.4.1
Timer Manager Low-level Programming Models
11.2.4.1.1
Surrounding Modules Global Initialization
11.2.4.1.2
Initialization Sequence
11.2.4.1.3
Real-time Operating Requirements
11.2.4.1.3.1
Timer Touch
11.2.4.1.3.2
Timer Disable
11.2.4.1.3.3
Timer Enable
11.2.4.1.4
Power Up/Power Down Sequence
11.2.5
Timer Manager Registers
11.2.5.1
TIMERMGR_CFG_CFG Registers
11.2.5.2
TIMERMGR_CFG_OES Registers
11.2.5.3
TIMERMGR_CFG_TIMERS Registers
11.3
Time Sync and Compare Events
11.3.1
Time Sync Architecture
11.3.1.1
Time Sync Architecture Overview
11.3.2
Time Sync Routers
11.3.2.1
Time Sync Routers Overview
11.3.2.2
Time Sync Routers Integration
11.3.2.2.1
TIMESYNC_INTRTR0 Integration
11.3.2.2.2
CMPEVT_INTRTR0 Integration
11.3.2.3
Time Sync Routers Registers
11.3.2.3.1
TIMESYNC_INTRTR0 Registers
11.3.2.3.2
CMPEVT_INTRTR0 Registers
11.3.3
Time Sync Event Sources
11.3.3.1
CMPEVT_INTRTR0 Event Map
11.3.3.2
TIMESYNC_INTRTR0 Event Map
11.3.3.3
DMSS0 Sync Event Map
11.3.3.4
PCIE1 Sync Event Map
11.3.3.5
MCU_CPSW0 Sync Event Map
11.3.3.6
CPSW0 Sync Event Map
11.3.3.7
I/O Sync Event Map
12
Peripherals
12.1
General Connectivity Peripherals
12.1.1
Analog-to-Digital Converter (ADC)
12.1.1.1
ADC Overview
12.1.1.1.1
ADC Features
12.1.1.1.2
ADC Not Supported Features
12.1.1.2
ADC Environment
12.1.1.2.1
ADC Interface Signals
12.1.1.3
ADC Integration
12.1.1.3.1
ADC Integration in MCU Domain
12.1.1.4
ADC Functional Description
12.1.1.4.1
ADC FSM Sequencer Functional Description
12.1.1.4.1.1
Step Enable
12.1.1.4.1.2
Step Configuration
12.1.1.4.1.2.1
One-Shot (Single) or Continuous Mode
12.1.1.4.1.2.2
Software- or Hardware-Enabled Steps
12.1.1.4.1.2.3
Averaging of Samples
12.1.1.4.1.2.4
Analog Multiplexer Input Select
12.1.1.4.1.2.5
Differential Control
12.1.1.4.1.2.6
FIFO Select
12.1.1.4.1.2.7
Range Check Interrupt Enable
12.1.1.4.1.3
Open Delay and Sample Delay
12.1.1.4.1.3.1
Open Delay
12.1.1.4.1.3.2
Sample Delay
12.1.1.4.1.4
Interrupts
12.1.1.4.1.5
Power Management
12.1.1.4.1.6
DMA Requests
12.1.1.4.2
ADC AFE Functional Description
12.1.1.4.2.1
AFE Functional Block Diagram
12.1.1.4.2.2
ADC GPI Integration
12.1.1.4.3
ADC FIFOs and DMA
12.1.1.4.3.1
FIFOs
12.1.1.4.3.2
DMA
12.1.1.4.4
ADC Error Correcting Code (ECC)
12.1.1.4.4.1
Testing ECC Error Injection
12.1.1.4.5
ADC Functional Internal Diagnostic Debug Mode
12.1.1.5
ADC Programming Guide
12.1.1.5.1
ADC Low-Level Programming Models
12.1.1.5.1.1
Global Initialization
12.1.1.5.1.1.1
Surrounding Modules Global Initialization
12.1.1.5.1.1.2
General Programming Model
12.1.1.5.1.2
During Operation
12.1.1.6
ADC Registers
12.1.2
General-Purpose Interface (GPIO)
12.1.2.1
GPIO Overview
12.1.2.1.1
GPIO Features
12.1.2.1.2
GPIO Not Supported Features
12.1.2.2
GPIO Environment
12.1.2.2.1
GPIO Interface Signals
12.1.2.3
GPIO Integration
12.1.2.3.1
GPIO Integration in WKUP Domain
12.1.2.3.2
GPIO Integration in MAIN Domain
12.1.2.4
GPIO Functional Description
12.1.2.4.1
GPIO Block Diagram
12.1.2.4.2
GPIO Function
12.1.2.4.3
GPIO Interrupt and Event Generation
12.1.2.4.3.1
Interrupt Enable (per Bank)
12.1.2.4.3.2
Trigger Configuration (per Bit)
12.1.2.4.3.3
Interrupt Status and Clear (per Bit)
12.1.2.4.4
GPIO Interrupt Connectivity
12.1.2.4.5
GPIO DeepSleep Mode
12.1.2.4.6
GPIO Emulation Halt Operation
12.1.2.5
GPIO Programming Guide
12.1.2.5.1
GPIO Low-Level Programming Models
12.1.2.5.1.1
Global Initialization
12.1.2.5.1.1.1
Surrounding Modules Global Initialization
12.1.2.5.1.1.2
GPIO Module Global Initialization
12.1.2.5.1.2
GPIO Operational Modes Configuration
12.1.2.5.1.2.1
GPIO Read Input Register
12.1.2.5.1.2.2
GPIO Set Bit Function
12.1.2.5.1.2.3
GPIO Clear Bit Function
12.1.2.6
GPIO Registers
12.1.3
Inter-Integrated Circuit (I2C) Interface
12.1.3.1
I2C Overview
12.1.3.1.1
I2C Features
12.1.3.1.2
I2C Not Supported Features
12.1.3.2
I2C Environment
12.1.3.2.1
I2C Typical Application
12.1.3.2.1.1
I2C Pins for Typical Connections in I2C Mode
12.1.3.2.1.2
I2C Interface Typical Connections
12.1.3.2.1.3
1501
12.1.3.2.2
I2C Typical Connection Protocol and Data Format
12.1.3.2.2.1
I2C Serial Data Format
12.1.3.2.2.2
I2C Data Validity
12.1.3.2.2.3
I2C Start and Stop Conditions
12.1.3.2.2.4
I2C Addressing
12.1.3.2.2.4.1
Data Transfer Formats in F/S Mode
12.1.3.2.2.4.2
Data Transfer Format in HS Mode
12.1.3.2.2.5
I2C Controller Transmitter
12.1.3.2.2.6
I2C Controller Receiver
12.1.3.2.2.7
I2C Target Transmitter
12.1.3.2.2.8
I2C Target Receiver
12.1.3.2.2.9
I2C Bus Arbitration
12.1.3.2.2.10
I2C Clock Generation and Synchronization
12.1.3.3
I2C Integration
12.1.3.3.1
I2C Integration in WKUP Domain
12.1.3.3.2
I2C Integration in MCU Domain
12.1.3.3.3
I2C Integration in MAIN Domain
12.1.3.4
I2C Functional Description
12.1.3.4.1
I2C Block Diagram
12.1.3.4.2
I2C Clocks
12.1.3.4.2.1
I2C Clocking
12.1.3.4.2.2
I2C Automatic Blocking of the I2C Clock Feature
12.1.3.4.3
I2C Software Reset
12.1.3.4.4
I2C Power Management
12.1.3.4.5
I2C Interrupt Requests
12.1.3.4.6
I2C Programmable Multitarget Channel Feature
12.1.3.4.7
I2C FIFO Management
12.1.3.4.7.1
I2C FIFO Interrupt Mode
12.1.3.4.7.2
I2C FIFO Polling Mode
12.1.3.4.7.3
I2C Draining Feature
12.1.3.4.8
I2C Noise Filter
12.1.3.4.9
I2C System Test Mode
12.1.3.5
I2C Programming Guide
12.1.3.5.1
I2C Low-Level Programming Models
12.1.3.5.1.1
I2C Programming Model
12.1.3.5.1.1.1
Main Program
12.1.3.5.1.1.1.1
Configure the Module Before Enabling the I2C Controller
12.1.3.5.1.1.1.2
Initialize the I2C Controller
12.1.3.5.1.1.1.3
Configure Target Address and the Data Control Register
12.1.3.5.1.1.1.4
Initiate a Transfer
12.1.3.5.1.1.1.5
Receive Data
12.1.3.5.1.1.1.6
Transmit Data
12.1.3.5.1.1.2
Interrupt Subroutine Sequence
12.1.3.5.1.1.3
Programming Flow-Diagrams
12.1.3.6
I2C Registers
12.1.4
Improved Inter-Integrated Circuit (I3C) Interface
12.1.4.1
I3C Overview
12.1.4.1.1
I3C Features
12.1.4.1.2
I3C Not Supported Features
12.1.4.2
I3C Environment
12.1.4.2.1
I3C Typical Application
12.1.4.2.1.1
I3C Pins for Typical Connections
12.1.4.2.1.2
I3C Interface Typical Connections
12.1.4.2.1.3
1555
12.1.4.3
I3C Integration
12.1.4.3.1
I3C Integration in MCU Domain
12.1.4.3.2
I3C Integration in MAIN Domain
12.1.4.4
I3C Functional Description
12.1.4.4.1
I3C Block Diagram
12.1.4.4.2
I3C Clock Configuration
12.1.4.4.2.1
Setting Base Frequencies
12.1.4.4.2.2
Asymmetric Push-Pull SCL Timing
12.1.4.4.2.3
Open-Drain SCL Timing
12.1.4.4.2.4
Changing Programmed Frequencies
12.1.4.4.3
I3C Interrupt Requests
12.1.4.4.4
I3C Power Configuration
12.1.4.4.5
I3C Dynamic Address Management
12.1.4.4.6
I3C Retaining Registers Space
12.1.4.4.7
I3C Dynamic Address Assignment Procedure
12.1.4.4.8
I3C Sending CCC Messages
12.1.4.4.9
I3C In-Band Interrupt
12.1.4.4.9.1
Regular I3C Slave In-Band Interrupt
12.1.4.4.9.2
Current Master Takeover In-Band Interrupt
12.1.4.4.10
I3C Hot-Join Request
12.1.4.4.11
I3C Immediate Commands
12.1.4.4.12
I3C Host Commands
12.1.4.4.13
I3C Sending Private Data in SDR Messages
12.1.4.4.13.1
SDR Private Write Message
12.1.4.4.13.2
SDR Private Read Message
12.1.4.4.13.3
SDR Payload Length Adjustment
12.1.4.5
I3C Programming Guide
12.1.4.5.1
I3C Power-On Programming Model
12.1.4.5.2
I3C Static Devices Programming
12.1.4.5.3
I3C DAA Procedure Initiation
12.1.4.5.4
I3C SDR Write Message Programming Model
12.1.4.5.5
I3C SDR Read Message Programming Model
12.1.4.5.6
I3C DDR Write Message Programming Model
12.1.4.5.7
I3C DDR Read Message Programming Model
12.1.4.6
I3C Registers
12.1.5
Multichannel Serial Peripheral Interface (MCSPI)
12.1.5.1
MCSPI Overview
12.1.5.1.1
SPI Features
12.1.5.1.2
MCSPI Not Supported Features
12.1.5.2
MCSPI Environment
12.1.5.2.1
Basic MCSPI Pins for Master Mode
12.1.5.2.2
Basic MCSPI Pins for Slave Mode
12.1.5.2.3
MCSPI Internal Connectivity
12.1.5.2.4
MCSPI Protocol and Data Format
12.1.5.2.4.1
Transfer Format
12.1.5.2.5
MCSPI in Controller Mode
12.1.5.2.6
MCSPI in Peripheral Mode
12.1.5.3
MCSPI Integration
12.1.5.3.1
MCSPI Integration in MCU Domain
12.1.5.3.2
MCSPI Integration in MAIN Domain
12.1.5.4
MCSPI Functional Description
12.1.5.4.1
SPI Block Diagram
12.1.5.4.2
MCSPI Reset
12.1.5.4.3
MCSPI Controller Mode
12.1.5.4.3.1
Controller Mode Features
12.1.5.4.3.2
Controller Transmit-and-Receive Mode (Full Duplex)
12.1.5.4.3.3
Controller Transmit-Only Mode (Half Duplex)
12.1.5.4.3.4
Controller Receive-Only Mode (Half Duplex)
12.1.5.4.3.5
Single-Channel Controller Mode
12.1.5.4.3.5.1
Programming Tips When Switching to Another Channel
12.1.5.4.3.5.2
Force SPIEN[i] Mode
12.1.5.4.3.5.3
Turbo Mode
12.1.5.4.3.6
Start-Bit Mode
12.1.5.4.3.7
Chip-Select Timing Control
12.1.5.4.3.8
Programmable MCSPI Clock (SPICLK)
12.1.5.4.3.8.1
Clock Ratio Granularity
12.1.5.4.4
MCSPI Peripheral Mode
12.1.5.4.4.1
Dedicated Resources
12.1.5.4.4.2
Peripheral Transmit-and-Receive Mode
12.1.5.4.4.3
Peripheral Transmit-Only Mode
12.1.5.4.4.4
Peripheral Receive-Only Mode
12.1.5.4.5
MCSPI 3-Pin or 4-Pin Mode
12.1.5.4.6
MCSPI FIFO Buffer Management
12.1.5.4.6.1
Buffer Almost Full
12.1.5.4.6.2
Buffer Almost Empty
12.1.5.4.6.3
End of Transfer Management
12.1.5.4.6.4
Multiple MCSPI Word Access
12.1.5.4.6.5
First MCSPI Word Delay
12.1.5.4.7
MCSPI Interrupts
12.1.5.4.7.1
Interrupt Events in Controller Mode
12.1.5.4.7.1.1
TXx_EMPTY
12.1.5.4.7.1.2
TXx_UNDERFLOW
12.1.5.4.7.1.3
RXx_ FULL
12.1.5.4.7.1.4
End Of Word Count
12.1.5.4.7.2
Interrupt Events in Peripheral Mode
12.1.5.4.7.2.1
TXx_EMPTY
12.1.5.4.7.2.2
TXx_UNDERFLOW
12.1.5.4.7.2.3
RXx_FULL
12.1.5.4.7.2.4
RX0_OVERFLOW
12.1.5.4.7.2.5
End Of Word Count
12.1.5.4.7.3
Interrupt-Driven Operation
12.1.5.4.7.4
Polling
12.1.5.4.8
MCSPI DMA Requests
12.1.5.4.9
MCSPI Power Saving Management
12.1.5.4.9.1
Normal Mode
12.1.5.4.9.2
Idle Mode
12.1.5.4.9.2.1
Force-Idle Mode
12.1.5.5
MCSPI Programming Guide
12.1.5.5.1
MCSPI Global Initialization
12.1.5.5.1.1
Surrounding Modules Global Initialization
12.1.5.5.1.2
MCSPI Global Initialization
12.1.5.5.1.2.1
Main Sequence – MCSPI Global Initialization
12.1.5.5.2
MCSPI Operational Mode Configuration
12.1.5.5.2.1
MCSPI Operational Modes
12.1.5.5.2.1.1
Common Transfer Sequence
12.1.5.5.2.1.2
End of Transfer Sequences
12.1.5.5.2.1.3
Transmit-and-Receive (Controller and Peripheral)
12.1.5.5.2.1.4
Transmit-Only (Controller and Peripheral)
12.1.5.5.2.1.4.1
Based on Interrupt Requests
12.1.5.5.2.1.4.2
Based on DMA Write Requests
12.1.5.5.2.1.5
Controller Normal Receive-Only
12.1.5.5.2.1.5.1
Based on Interrupt Requests
12.1.5.5.2.1.5.2
Based on DMA Read Requests
12.1.5.5.2.1.6
Controller Turbo Receive-Only
12.1.5.5.2.1.6.1
Based on Interrupt Requests
12.1.5.5.2.1.6.2
Based on DMA Read Requests
12.1.5.5.2.1.7
Peripheral Receive-Only
12.1.5.5.2.1.8
Transfer Procedures With FIFO
12.1.5.5.2.1.8.1
Common Transfer Sequence in FIFO Mode
12.1.5.5.2.1.8.2
End of Transfer Sequences in FIFO Mode
12.1.5.5.2.1.8.3
Transmit-and-Receive With Word Count
12.1.5.5.2.1.8.4
Transmit-and-Receive Without Word Count
12.1.5.5.2.1.8.5
Transmit-Only
12.1.5.5.2.1.8.6
Receive-Only With Word Count
12.1.5.5.2.1.8.7
Receive-Only Without Word Count
12.1.5.5.2.1.9
Common Transfer Procedures Without FIFO – Polling Method
12.1.5.5.2.1.9.1
Receive-Only Procedure – Polling Method
12.1.5.5.2.1.9.2
Receive-Only Procedure – Interrupt Method
12.1.5.5.2.1.9.3
Transmit-Only Procedure – Polling Method
12.1.5.5.2.1.9.4
Transmit-and-Receive Procedure – Polling Method
12.1.5.6
MCSPI Registers
12.1.6
Universal Asynchronous Receiver/Transmitter (UART)
12.1.6.1
UART Overview
12.1.6.1.1
UART Features
12.1.6.1.2
IrDA Features
12.1.6.1.3
CIR Features
12.1.6.1.4
UART Not Supported Features
12.1.6.2
UART Environment
12.1.6.2.1
UART Functional Interfaces
12.1.6.2.1.1
System Using UART Communication With Hardware Handshake
12.1.6.2.1.2
UART Interface Description
12.1.6.2.1.3
UART Protocol and Data Format
12.1.6.2.1.4
UART 9-bit Mode Data Format
12.1.6.2.2
RS-485 Functional Interfaces
12.1.6.2.2.1
System Using RS-485 Communication
12.1.6.2.2.2
RS-485 Interface Description
12.1.6.2.3
IrDA Functional Interfaces
12.1.6.2.3.1
System Using IrDA Communication Protocol
12.1.6.2.3.2
IrDA Interface Description
12.1.6.2.3.3
IrDA Protocol and Data Format
12.1.6.2.3.3.1
SIR Mode
12.1.6.2.3.3.1.1
Frame Format
12.1.6.2.3.3.1.2
Asynchronous Transparency
12.1.6.2.3.3.1.3
Abort Sequence
12.1.6.2.3.3.1.4
Pulse Shaping
12.1.6.2.3.3.1.5
Encoder
12.1.6.2.3.3.1.6
Decoder
12.1.6.2.3.3.1.7
IR Address Checking
12.1.6.2.3.3.2
SIR Free-Format Mode
12.1.6.2.3.3.3
MIR Mode
12.1.6.2.3.3.3.1
MIR Encoder/Decoder
12.1.6.2.3.3.3.2
SIP Generation
12.1.6.2.3.3.4
FIR Mode
12.1.6.2.4
CIR Functional Interfaces
12.1.6.2.4.1
System Using CIR Communication Protocol With Remote Control
12.1.6.2.4.2
CIR Interface Description
12.1.6.2.4.3
CIR Protocol and Data Format
12.1.6.2.4.3.1
Carrier Modulation
12.1.6.2.4.3.2
Pulse Duty Cycle
12.1.6.2.4.3.3
Consumer IR Encoding/Decoding
12.1.6.3
UART Integration
12.1.6.3.1
UART Integration in WKUP Domain
12.1.6.3.2
UART Integration in MCU Domain
12.1.6.3.3
UART Integration in MAIN Domain
12.1.6.4
UART Functional Description
12.1.6.4.1
UART Block Diagram
12.1.6.4.2
UART Clock Configuration
12.1.6.4.3
UART Software Reset
12.1.6.4.3.1
Independent TX/RX
12.1.6.4.4
UART Power Management
12.1.6.4.4.1
UART Mode Power Management
12.1.6.4.4.1.1
Module Power Saving
12.1.6.4.4.1.2
System Power Saving
12.1.6.4.4.2
IrDA Mode Power Management
12.1.6.4.4.2.1
Module Power Saving
12.1.6.4.4.2.2
System Power Saving
12.1.6.4.4.3
CIR Mode Power Management
12.1.6.4.4.3.1
Module Power Saving
12.1.6.4.4.3.2
System Power Saving
12.1.6.4.4.4
Local Power Management
12.1.6.4.5
UART Interrupt Requests
12.1.6.4.5.1
UART Mode Interrupt Management
12.1.6.4.5.1.1
UART Interrupts
12.1.6.4.5.1.2
Wake-Up Interrupt
12.1.6.4.5.2
IrDA Mode Interrupt Management
12.1.6.4.5.2.1
IrDA Interrupts
12.1.6.4.5.2.2
Wake-Up Interrupts
12.1.6.4.5.3
CIR Mode Interrupt Management
12.1.6.4.5.3.1
CIR Interrupts
12.1.6.4.5.3.2
Wake-Up Interrupts
12.1.6.4.6
UART FIFO Management
12.1.6.4.6.1
FIFO Trigger
12.1.6.4.6.1.1
Transmit FIFO Trigger
12.1.6.4.6.1.2
Receive FIFO Trigger
12.1.6.4.6.2
FIFO Interrupt Mode
12.1.6.4.6.3
FIFO Polled Mode Operation
12.1.6.4.6.4
FIFO DMA Mode Operation
12.1.6.4.6.4.1
DMA sequence to disable TX DMA
12.1.6.4.6.4.2
DMA Transfers (DMA Mode 1, 2, or 3)
12.1.6.4.6.4.3
DMA Transmission
12.1.6.4.6.4.4
DMA Reception
12.1.6.4.7
UART Mode Selection
12.1.6.4.7.1
Register Access Modes
12.1.6.4.7.1.1
Operational Mode and Configuration Modes
12.1.6.4.7.1.2
Register Access Submode
12.1.6.4.7.1.3
Registers Available for the Register Access Modes
12.1.6.4.7.2
UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
12.1.6.4.7.2.1
Registers Available for the UART Function
12.1.6.4.7.2.2
Registers Available for the IrDA Function
12.1.6.4.7.2.3
Registers Available for the CIR Function
12.1.6.4.8
UART Protocol Formatting
12.1.6.4.8.1
UART Mode
12.1.6.4.8.1.1
UART Clock Generation: Baud Rate Generation
12.1.6.4.8.1.2
Choosing the Appropriate Divisor Value
12.1.6.4.8.1.3
UART Data Formatting
12.1.6.4.8.1.3.1
Frame Formatting
12.1.6.4.8.1.3.2
Hardware Flow Control
12.1.6.4.8.1.3.3
Software Flow Control
1.6.4.8.1.3.3.1
Receive (RX)
1.6.4.8.1.3.3.2
Transmit (TX)
12.1.6.4.8.1.3.4
Autobauding Modes
12.1.6.4.8.1.3.5
Error Detection
12.1.6.4.8.1.3.6
Overrun During Receive
12.1.6.4.8.1.3.7
Time-Out and Break Conditions
1.6.4.8.1.3.7.1
Time-Out Counter
1.6.4.8.1.3.7.2
Break Condition
12.1.6.4.8.2
RS-485 Mode
12.1.6.4.8.2.1
RS-485 External Transceiver Direction Control
12.1.6.4.8.3
IrDA Mode
12.1.6.4.8.3.1
IrDA Clock Generation: Baud Generator
12.1.6.4.8.3.2
Choosing the Appropriate Divisor Value
12.1.6.4.8.3.3
IrDA Data Formatting
12.1.6.4.8.3.3.1
IR RX Polarity Control
12.1.6.4.8.3.3.2
IrDA Reception Control
12.1.6.4.8.3.3.3
IR Address Checking
12.1.6.4.8.3.3.4
Frame Closing
12.1.6.4.8.3.3.5
Store and Controlled Transmission
12.1.6.4.8.3.3.6
Error Detection
12.1.6.4.8.3.3.7
Underrun During Transmission
12.1.6.4.8.3.3.8
Overrun During Receive
12.1.6.4.8.3.3.9
Status FIFO
12.1.6.4.8.3.3.10
Multi-drop Parity Mode with Address Match
12.1.6.4.8.3.3.11
Time-guard
12.1.6.4.8.3.4
SIR Mode Data Formatting
12.1.6.4.8.3.4.1
Abort Sequence
12.1.6.4.8.3.4.2
Pulse Shaping
12.1.6.4.8.3.4.3
SIR Free Format Programming
12.1.6.4.8.3.5
MIR and FIR Mode Data Formatting
12.1.6.4.8.4
CIR Mode
12.1.6.4.8.4.1
CIR Mode Clock Generation
12.1.6.4.8.4.2
CIR Data Formatting
12.1.6.4.8.4.2.1
IR RX Polarity Control
12.1.6.4.8.4.2.2
CIR Transmission
12.1.6.4.8.4.2.3
CIR Reception
12.1.6.5
UART Programming Guide
12.1.6.5.1
UART Global Initialization
12.1.6.5.1.1
Surrounding Modules Global Initialization
12.1.6.5.1.2
UART Module Global Initialization
12.1.6.5.2
UART Mode selection
12.1.6.5.3
UART Submode selection
12.1.6.5.4
UART Load FIFO trigger and DMA mode settings
12.1.6.5.4.1
DMA mode Settings
12.1.6.5.4.2
FIFO Trigger Settings
12.1.6.5.5
UART Protocol, Baud rate and interrupt settings
12.1.6.5.5.1
Baud rate settings
12.1.6.5.5.2
Interrupt settings
12.1.6.5.5.3
Protocol settings
12.1.6.5.5.4
UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
12.1.6.5.5.5
UART Multi-drop Parity Address Match Mode Configuration
12.1.6.5.6
UART Hardware and Software Flow Control Configuration
12.1.6.5.6.1
Hardware Flow Control Configuration
12.1.6.5.6.2
Software Flow Control Configuration
12.1.6.5.7
IrDA Programming Model
12.1.6.5.7.1
SIR mode
12.1.6.5.7.1.1
Receive
12.1.6.5.7.1.2
Transmit
12.1.6.5.7.2
MIR mode
12.1.6.5.7.2.1
Receive
12.1.6.5.7.2.2
Transmit
12.1.6.5.7.3
FIR mode
12.1.6.5.7.3.1
Receive
12.1.6.5.7.3.2
Transmit
12.1.6.6
UART Registers
12.2
High-speed Serial Interfaces
12.2.1
Gigabit Ethernet MAC (MCU_CPSW0)
12.2.1.1
MCU_CPSW0 Overview
12.2.1.1.1
MCU_CPSW0 Features
12.2.1.1.2
MCU_CPSW0 Not Supported Features
12.2.1.1.3
Terminology
12.2.1.2
MCU_CPSW0 Environment
12.2.1.2.1
MCU_CPSW0 RMII Interface
12.2.1.2.2
MCU_CPSW0 RGMII Interface
12.2.1.3
MCU_CPSW0 Integration
12.2.1.4
MCU_CPSW0 Functional Description
12.2.1.4.1
Functional Block Diagram
12.2.1.4.2
CPSW Ports
12.2.1.4.2.1
Interface Mode Selection
12.2.1.4.3
Clocking
12.2.1.4.3.1
Subsystem Clocking
12.2.1.4.3.2
Interface Clocking
12.2.1.4.3.2.1
RGMII Interface Clocking
12.2.1.4.3.2.2
RMII Interface Clocking
12.2.1.4.3.2.3
MDIO Clocking
12.2.1.4.4
Software IDLE
12.2.1.4.5
Interrupt Functionality
12.2.1.4.5.1
EVNT_PEND Interrupt
12.2.1.4.5.2
Statistics Interrupt (STAT_PEND0)
12.2.1.4.5.3
ECC DED Level Interrupt (ECC_DED_INT)
12.2.1.4.5.4
ECC SEC Level Interrupt (ECC_SEC_INT)
12.2.1.4.5.5
MDIO Interrupts
12.2.1.4.6
CPSW_2G
12.2.1.4.6.1
Address Lookup Engine (ALE)
12.2.1.4.6.1.1
Error Handling
12.2.1.4.6.1.2
Bypass Operations
12.2.1.4.6.1.3
OUI Deny or Accept
12.2.1.4.6.1.4
Statistics Counting
12.2.1.4.6.1.5
Automotive Security Features
12.2.1.4.6.1.6
CPSW Switching Solutions
12.2.1.4.6.1.6.1
Basics of 2-port Switch Type
12.2.1.4.6.1.7
VLAN Routing and OAM Operations
12.2.1.4.6.1.7.1
InterVLAN Routing
12.2.1.4.6.1.7.2
OAM Operations
12.2.1.4.6.1.8
Supervisory packets
12.2.1.4.6.1.9
Address Table Entry
12.2.1.4.6.1.9.1
Free Table Entry
12.2.1.4.6.1.9.2
Multicast Address Table Entry
12.2.1.4.6.1.9.3
VLAN/Multicast Address Table Entry
12.2.1.4.6.1.9.4
Unicast Address Table Entry
12.2.1.4.6.1.9.5
OUI Unicast Address Table Entry
12.2.1.4.6.1.9.6
VLAN/Unicast Address Table Entry
12.2.1.4.6.1.9.7
VLAN Table Entry
12.2.1.4.6.1.10
ALE Policing and Classification
12.2.1.4.6.1.10.1
ALE Classification
2.1.4.6.1.10.1.1
Classifier to CPPI Transmit Flow ID Mapping
12.2.1.4.6.1.11
DSCP
12.2.1.4.6.1.12
Packet Forwarding Processes
12.2.1.4.6.1.12.1
Ingress Filtering Process
12.2.1.4.6.1.12.2
VLAN_Aware Lookup Process
12.2.1.4.6.1.12.3
Egress Process
12.2.1.4.6.1.12.4
Learning/Updating/Touching Processes
2.1.4.6.1.12.4.1
Learning Process
2.1.4.6.1.12.4.2
Updating Process
2.1.4.6.1.12.4.3
Touching Process
12.2.1.4.6.1.13
VLAN Aware Mode
12.2.1.4.6.1.14
VLAN Unaware Mode
12.2.1.4.6.2
Packet Priority Handling
12.2.1.4.6.2.1
Priority Mapping and Transmit VLAN Priority
12.2.1.4.6.3
CPPI Port Ingress
12.2.1.4.6.4
Packet CRC Handling
12.2.1.4.6.4.1
Transmit VLAN Processing
12.2.1.4.6.4.1.1
Untagged Packets (No VLAN or Priority Tag Header)
12.2.1.4.6.4.1.2
Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
12.2.1.4.6.4.1.3
VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
12.2.1.4.6.4.2
Ethernet Port Ingress Packet CRC
12.2.1.4.6.4.3
Ethernet Port Egress Packet CRC
12.2.1.4.6.4.4
CPPI Port Ingress Packet CRC
12.2.1.4.6.4.5
CPPI Port Egress Packet CRC
12.2.1.4.6.5
FIFO Memory Control
12.2.1.4.6.6
FIFO Transmit Queue Control
12.2.1.4.6.6.1
CPPI Port Receive Rate Limiting
12.2.1.4.6.6.2
Ethernet Port Transmit Rate Limiting
12.2.1.4.6.7
Intersperced Express Traffic (IET – P802.3br/D2.0)
12.2.1.4.6.7.1
IET Configuration
12.2.1.4.6.8
Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
12.2.1.4.6.8.1
Enhanced Scheduled Traffic Overview
12.2.1.4.6.8.2
Enhanced Scheduled Traffic Fetch RAM
12.2.1.4.6.8.3
Enhanced Scheduled Traffic Time Interval
12.2.1.4.6.8.4
Enhanced Scheduled Traffic Fetch Values
12.2.1.4.6.8.5
Enhanced Scheduled Traffic Packet Fill
12.2.1.4.6.8.6
Enhanced Scheduled Traffic Time Stamp
12.2.1.4.6.8.7
Enhanced Scheduled Traffic Packets Per Priority
12.2.1.4.6.9
Audio Video Bridging
12.2.1.4.6.9.1
IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
12.2.1.4.6.9.1.1
IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
2.1.4.6.9.1.1.1
Cross-timestamping and Presentation Timestamps
12.2.1.4.6.9.1.2
IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
12.2.1.4.6.9.2
IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
12.2.1.4.6.9.2.1
Configuring the Device for 802.1Qav Operation
12.2.1.4.6.10
Ethernet MAC Sliver
12.2.1.4.6.10.1
1945
12.2.1.4.6.10.1.1
1946
2.1.4.6.10.1.1.1
CRC Insertion
2.1.4.6.10.1.1.2
MTXER
2.1.4.6.10.1.1.3
Adaptive Performance Optimization (APO)
2.1.4.6.10.1.1.4
Inter-Packet-Gap Enforcement
2.1.4.6.10.1.1.5
Back Off
2.1.4.6.10.1.1.6
Programmable Transmit Inter-Packet Gap
2.1.4.6.10.1.1.7
Speed, Duplex and Pause Frame Support Negotiation
12.2.1.4.6.10.2
RMII Interface
12.2.1.4.6.10.2.1
Features
12.2.1.4.6.10.2.2
RMII Receive (RX)
12.2.1.4.6.10.2.3
RMII Transmit (TX)
12.2.1.4.6.10.3
RGMII Interface
12.2.1.4.6.10.3.1
Features
12.2.1.4.6.10.3.2
RGMII Receive (RX)
12.2.1.4.6.10.3.3
In-Band Mode of Operation
12.2.1.4.6.10.3.4
Forced Mode of Operation
12.2.1.4.6.10.3.5
RGMII Transmit (TX)
12.2.1.4.6.10.4
Frame Classification
12.2.1.4.6.10.5
Receive FIFO Architecture
12.2.1.4.6.11
Embedded Memories
12.2.1.4.6.12
Memory Error Detection and Correction
12.2.1.4.6.12.1
Packet Header ECC
12.2.1.4.6.12.2
Packet Protect CRC
12.2.1.4.6.12.3
Aggregator RAM Control
12.2.1.4.6.13
Ethernet Port Flow Control
12.2.1.4.6.13.1
Ethernet Receive Flow Control
12.2.1.4.6.13.1.1
Collision Based Receive Buffer Flow Control
12.2.1.4.6.13.1.2
IEEE 802.3X Based Receive Flow Control
12.2.1.4.6.13.2
Flow Control Trigger
12.2.1.4.6.13.3
Ethernet Transmit Flow Control
12.2.1.4.6.14
Energy Efficient Ethernet Support (802.3az)
12.2.1.4.6.15
Ethernet Switch Latency
12.2.1.4.6.16
MAC Emulation Control
12.2.1.4.6.17
MAC Command IDLE
12.2.1.4.6.18
CPSW Network Statistics
12.2.1.4.6.18.1
Rx-only Statistics Descriptions
12.2.1.4.6.18.1.1
Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
12.2.1.4.6.18.1.2
Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
12.2.1.4.6.18.1.3
Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
12.2.1.4.6.18.1.4
Pause Rx Frames (Offset = 3A20Ch - Port 1)
12.2.1.4.6.18.1.5
Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
12.2.1.4.6.18.1.6
Rx Align/Code Errors (Offset = 3A214h - Port 1)
12.2.1.4.6.18.1.7
Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
12.2.1.4.6.18.1.8
Rx Jabbers (Offset = 3A21Ch - Port 1)
12.2.1.4.6.18.1.9
Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
12.2.1.4.6.18.1.10
Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
12.2.1.4.6.18.1.11
RX IPG Error (Offset = 3A25Ch - Port 1)
12.2.1.4.6.18.1.12
ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
12.2.1.4.6.18.1.13
ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
12.2.1.4.6.18.1.14
Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
12.2.1.4.6.18.1.15
Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
12.2.1.4.6.18.1.16
Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
12.2.1.4.6.18.1.17
Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
12.2.1.4.6.18.1.18
ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
12.2.1.4.6.18.1.19
ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
2.1.4.6.18.1.19.1
ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
2.1.4.6.18.1.19.2
Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
2.1.4.6.18.1.19.3
ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
2.1.4.6.18.1.19.4
ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
2.1.4.6.18.1.19.5
ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
2.1.4.6.18.1.19.6
ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
2.1.4.6.18.1.19.7
ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
2.1.4.6.18.1.19.8
ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
2.1.4.6.18.1.19.9
ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
2.1.4.6.18.1.19.10
ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
2.1.4.6.18.1.19.11
ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
12.2.1.4.6.18.2
ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
12.2.1.4.6.18.3
ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
12.2.1.4.6.18.4
IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
12.2.1.4.6.18.5
IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
12.2.1.4.6.18.6
IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
12.2.1.4.6.18.7
IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
12.2.1.4.6.18.8
Tx-only Statistics Descriptions
12.2.1.4.6.18.8.1
Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
12.2.1.4.6.18.8.2
Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
12.2.1.4.6.18.8.3
Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
12.2.1.4.6.18.8.4
Pause Tx Frames (Offset = 3A240h - Port 1)
12.2.1.4.6.18.8.5
Deferred Tx Frames (Offset = 3A244h - Port 1)
12.2.1.4.6.18.8.6
Collisions (Offset = 3A248h - Port 1)
12.2.1.4.6.18.8.7
Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
12.2.1.4.6.18.8.8
Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
12.2.1.4.6.18.8.9
Excessive Collisions (Offset = 3A254h - Port 1)
12.2.1.4.6.18.8.10
Late Collisions (Offset = 3A258h - Port 1)
12.2.1.4.6.18.8.11
Carrier Sense Errors (Offset = 3A260h - Port 1)
12.2.1.4.6.18.8.12
Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
12.2.1.4.6.18.8.13
Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
12.2.1.4.6.18.8.14
Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
12.2.1.4.6.18.8.15
Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
12.2.1.4.6.18.8.16
IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
12.2.1.4.6.18.8.17
IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
12.2.1.4.6.18.9
Rx- and Tx (Shared) Statistics Descriptions
12.2.1.4.6.18.9.1
Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
12.2.1.4.6.18.9.2
Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
12.2.1.4.6.18.9.3
Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
12.2.1.4.6.18.9.4
Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
12.2.1.4.6.18.9.5
Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
12.2.1.4.6.18.9.6
Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
12.2.1.4.6.18.9.7
Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
12.2.1.4.6.18.10
2045
12.2.1.4.7
Common Platform Time Sync (CPTS)
12.2.1.4.7.1
MCU_CPSW0 CPTS Integration
12.2.1.4.7.2
CPTS Architecture
12.2.1.4.7.3
CPTS Initialization
12.2.1.4.7.4
32-bit Time Stamp Value
12.2.1.4.7.5
64-bit Time Stamp Value
12.2.1.4.7.6
64-Bit Timestamp Nudge
12.2.1.4.7.7
64-bit Timestamp PPM
12.2.1.4.7.8
Event FIFO
12.2.1.4.7.9
Timestamp Compare Output
12.2.1.4.7.9.1
Non-Toggle Mode: 32-bit
12.2.1.4.7.9.2
Non-Toggle Mode: 64-bit
12.2.1.4.7.9.3
Toggle Mode: 32-bit
12.2.1.4.7.9.4
Toggle Mode: 64-bit
12.2.1.4.7.10
Timestamp Sync Output
12.2.1.4.7.11
Timestamp GENFn Output
12.2.1.4.7.11.1
GENFn Nudge
12.2.1.4.7.11.2
GENFn PPM
12.2.1.4.7.12
Timestamp ESTFn
12.2.1.4.7.13
Time Sync Events
12.2.1.4.7.13.1
Time Stamp Push Event
12.2.1.4.7.13.2
Time Stamp Counter Rollover Event (32-bit mode only)
12.2.1.4.7.13.3
Time Stamp Counter Half-rollover Event (32-bit mode only)
12.2.1.4.7.13.4
Hardware Time Stamp Push Event
12.2.1.4.7.13.5
Ethernet Port Events
12.2.1.4.7.13.5.1
Ethernet Port Receive Event
12.2.1.4.7.13.5.2
Ethernet Port Transmit Event
12.2.1.4.7.13.5.3
2073
12.2.1.4.7.14
Timestamp Compare Event
12.2.1.4.7.14.1
32-Bit Mode
12.2.1.4.7.14.2
64-Bit Mode
12.2.1.4.7.15
Host Transmit Event
12.2.1.4.7.16
CPTS Interrupt Handling
12.2.1.4.8
CPPI Streaming Packet Interface
12.2.1.4.8.1
Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
12.2.1.4.8.2
Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
12.2.1.4.8.3
CPPI Checksum Offload
12.2.1.4.8.3.1
CPPI Transmit Checksum Offload
12.2.1.4.8.3.1.1
IPV4 UDP
12.2.1.4.8.3.1.2
IPV4 TCP
12.2.1.4.8.3.1.3
IPV6 UDP
12.2.1.4.8.3.1.4
IPV6 TCP
12.2.1.4.8.4
CPPI Receive Checksum Offload
12.2.1.4.8.5
Egress Packet Operations
12.2.1.4.9
MII Management Interface (MDIO)
12.2.1.4.9.1
MDIO Frame Formats
12.2.1.4.9.2
MDIO Functional Description
12.2.1.5
MCU_CPSW0 Programming Guide
12.2.1.5.1
Initialization and Configuration of CPSW Subsystem
12.2.1.5.2
CPSW Reset
12.2.1.5.3
MDIO Software Interface
12.2.1.5.3.1
Initializing the MDIO Module
12.2.1.5.3.2
Writing Data To a PHY Register
12.2.1.5.3.3
Reading Data From a PHY Register
12.2.1.6
MCU_CPSW0 Registers
12.2.1.6.1
MCU_CPSW0_NUSS Subsystem (SS) Registers
12.2.1.6.2
MCU_CPSW0_SGMII Registers
12.2.1.6.3
MCU_CPSW0_MDIO Registers
12.2.1.6.4
MCU_CPSW0_CPTS Registers
12.2.1.6.5
MCU_CPSW0_CONTROL Registers
12.2.1.6.6
MCU_CPSW0_CPINT Registers
12.2.1.6.7
MCU_CPSW0_RAM Registers
12.2.1.6.8
MCU_CPSW0_STAT0 Registers
12.2.1.6.9
MCU_CPSW0_STAT1 Registers
12.2.1.6.10
MCU_CPSW0_ALE Registers
12.2.1.6.11
MCU_CPSW0_ECC Registers
12.2.2
Gigabit Ethernet Switch (CPSW0)
12.2.2.1
CPSW0 Overview
12.2.2.1.1
CPSW0 Features
12.2.2.1.2
CPSW0 Not Supported Features
12.2.2.1.3
Terminology
12.2.2.2
CPSW0 Environment
12.2.2.2.1
CPSW0 RMII Interface
12.2.2.2.2
CPSW0 RGMII Interface
12.2.2.3
CPSW0 Integration
12.2.2.4
CPSW0 Functional Description
12.2.2.4.1
Functional Block Diagram
12.2.2.4.2
CPSW Ports
12.2.2.4.2.1
Interface Mode Selection
12.2.2.4.3
Clocking
12.2.2.4.3.1
Subsystem Clocking
12.2.2.4.3.2
Interface Clocking
12.2.2.4.3.2.1
RGMII Interface Clocking
12.2.2.4.3.2.2
RMII Interface Clocking
12.2.2.4.3.2.3
MDIO Clocking
12.2.2.4.4
Software IDLE
12.2.2.4.5
Interrupt Functionality
12.2.2.4.5.1
EVNT_PEND Interrupt
12.2.2.4.5.2
Statistics Interrupt (STAT_PEND0)
12.2.2.4.5.3
ECC DED Level Interrupt (ECC_DED_INT)
12.2.2.4.5.4
ECC SEC Level Interrupt (ECC_SEC_INT)
12.2.2.4.5.5
MDIO Interrupts
12.2.2.4.6
CPSW_5X
12.2.2.4.6.1
Address Lookup Engine (ALE)
12.2.2.4.6.1.1
Error Handling
12.2.2.4.6.1.2
Bypass Operations
12.2.2.4.6.1.3
OUI Deny or Accept
12.2.2.4.6.1.4
Statistics Counting
12.2.2.4.6.1.5
Automotive Security Features
12.2.2.4.6.1.6
CPSW Switching Solutions
12.2.2.4.6.1.6.1
Basics of 5-port Switch Type
12.2.2.4.6.1.7
VLAN Routing and OAM Operations
12.2.2.4.6.1.7.1
InterVLAN Routing
12.2.2.4.6.1.7.2
OAM Operations
12.2.2.4.6.1.8
Supervisory packets
12.2.2.4.6.1.9
Address Table Entry
12.2.2.4.6.1.9.1
Free Table Entry
12.2.2.4.6.1.9.2
Multicast Address Table Entry (Bit 40 == 0)
12.2.2.4.6.1.9.3
Multicast Address Table Entry (Bit 40 == 1)
12.2.2.4.6.1.9.4
VLAN Unicast Address Table Entry (Bit 40 == 0)
12.2.2.4.6.1.9.5
OUI Unicast Address Table Entry
12.2.2.4.6.1.9.6
VLAN/Unicast Address Table Entry (Bit 40 == 0)
12.2.2.4.6.1.9.7
VLAN/ Multicast Address Table Entry (Bit 40 == 1)
12.2.2.4.6.1.9.8
Inner VLAN Table Entry
12.2.2.4.6.1.9.9
Outer VLAN Table Entry
12.2.2.4.6.1.9.10
EtherType Table Entry
12.2.2.4.6.1.9.11
IPv4 Table Entry
12.2.2.4.6.1.9.12
IPv6 Table Entry High
12.2.2.4.6.1.9.13
IPv6 Table Entry Low
12.2.2.4.6.1.10
Multicast Address
12.2.2.4.6.1.10.1
Multicast Ranges
12.2.2.4.6.1.11
Supervisory Packets
12.2.2.4.6.1.12
Aging and Auto Aging
12.2.2.4.6.1.13
ALE Policing and Classification
12.2.2.4.6.1.13.1
ALE Policing
12.2.2.4.6.1.13.2
Classifier to Host Thread Mapping
12.2.2.4.6.1.13.3
ALE Classification
2.2.4.6.1.13.3.1
Classifier to CPPI Transmit Flow ID Mapping
12.2.2.4.6.1.14
Mirroring
12.2.2.4.6.1.15
Trunking
12.2.2.4.6.1.16
DSCP
12.2.2.4.6.1.17
Packet Forwarding Processes
12.2.2.4.6.1.17.1
Ingress Filtering Process
12.2.2.4.6.1.17.2
VLAN_Aware Lookup Process
12.2.2.4.6.1.17.3
Egress Process
12.2.2.4.6.1.17.4
Learning/Updating/Touching Processes
2.2.4.6.1.17.4.1
Learning Process
2.2.4.6.1.17.4.2
Updating Process
2.2.4.6.1.17.4.3
Touching Process
12.2.2.4.6.1.18
VLAN Aware Mode
12.2.2.4.6.1.19
VLAN Unaware Mode
12.2.2.4.6.2
Packet Priority Handling
12.2.2.4.6.2.1
Priority Mapping and Transmit VLAN Priority
12.2.2.4.6.3
CPPI Port Ingress
12.2.2.4.6.4
Packet CRC Handling
12.2.2.4.6.4.1
Transmit VLAN Processing
12.2.2.4.6.4.1.1
Untagged Packets (No VLAN or Priority Tag Header)
12.2.2.4.6.4.1.2
Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
12.2.2.4.6.4.1.3
VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
12.2.2.4.6.4.2
Ethernet Port Ingress Packet CRC
12.2.2.4.6.4.3
Ethernet Port Egress Packet CRC
12.2.2.4.6.4.4
CPPI Port Ingress Packet CRC
12.2.2.4.6.4.5
CPPI Port Egress Packet CRC
12.2.2.4.6.5
FIFO Memory Control
12.2.2.4.6.6
FIFO Transmit Queue Control
12.2.2.4.6.6.1
CPPI Port Receive Rate Limiting
12.2.2.4.6.6.2
Ethernet Port Transmit Rate Limiting
12.2.2.4.6.7
Intersperced Express Traffic (IET – P802.3br/D2.0)
12.2.2.4.6.7.1
IET Configuration
12.2.2.4.6.8
Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
12.2.2.4.6.8.1
Enhanced Scheduled Traffic Overview
12.2.2.4.6.8.2
Enhanced Scheduled Traffic Fetch RAM
12.2.2.4.6.8.3
Enhanced Scheduled Traffic Time Interval
12.2.2.4.6.8.4
Enhanced Scheduled Traffic Fetch Values
12.2.2.4.6.8.5
Enhanced Scheduled Traffic Packet Fill
12.2.2.4.6.8.6
Enhanced Scheduled Traffic Time Stamp
12.2.2.4.6.9
Audio Video Bridging
12.2.2.4.6.9.1
IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
12.2.2.4.6.9.1.1
IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
2.2.4.6.9.1.1.1
Cross-timestamping and Presentation Timestamps
12.2.2.4.6.9.1.2
IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
12.2.2.4.6.9.2
IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
12.2.2.4.6.9.2.1
Configuring the Device for 802.1Qav Operation
12.2.2.4.6.10
Ethernet MAC Sliver
12.2.2.4.6.10.1
CRC Insertion
12.2.2.4.6.10.2
MTXER
12.2.2.4.6.10.3
Adaptive Performance Optimization (APO)
12.2.2.4.6.10.4
Inter-Packet-Gap Enforcement
12.2.2.4.6.10.5
Back Off
12.2.2.4.6.10.6
Programmable Transmit Inter-Packet Gap
12.2.2.4.6.10.7
Speed, Duplex and Pause Frame Support Negotiation
12.2.2.4.6.10.8
RMII Interface
12.2.2.4.6.10.8.1
Features
12.2.2.4.6.10.8.2
RMII Receive (RX)
12.2.2.4.6.10.8.3
RMII Transmit (TX)
12.2.2.4.6.10.9
RGMII Interface
12.2.2.4.6.10.9.1
Features
12.2.2.4.6.10.9.2
RGMII Receive (RX)
12.2.2.4.6.10.9.3
In-Band Mode of Operation
12.2.2.4.6.10.9.4
Forced Mode of Operation
12.2.2.4.6.10.9.5
RGMII Transmit (TX)
12.2.2.4.6.10.10
Frame Classification
12.2.2.4.6.10.11
Receive FIFO Architecture
12.2.2.4.6.11
Embedded Memories
12.2.2.4.6.12
Memory Error Detection and Correction
12.2.2.4.6.12.1
Packet Header ECC
12.2.2.4.6.12.2
Packet Protect CRC
12.2.2.4.6.12.3
Aggregator RAM Control
12.2.2.4.6.13
Ethernet Port Flow Control
12.2.2.4.6.13.1
Ethernet Receive Flow Control
12.2.2.4.6.13.1.1
Collision Based Receive Buffer Flow Control
12.2.2.4.6.13.1.2
IEEE 802.3X Based Receive Flow Control
12.2.2.4.6.13.2
Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
12.2.2.4.6.13.3
Ethernet Transmit Flow Control
12.2.2.4.6.14
PFC Trigger Rules
12.2.2.4.6.14.1
Destination Based Rule
12.2.2.4.6.14.2
Sum of Outflows Rule
12.2.2.4.6.14.3
Sum of Blocks Per Port Rule
12.2.2.4.6.14.4
Sum of Blocks Total Rule
12.2.2.4.6.14.5
Top of Receive FIFO Rule
12.2.2.4.6.15
Energy Efficient Ethernet Support (802.3az)
12.2.2.4.6.16
Ethernet Switch Latency
12.2.2.4.6.17
MAC Emulation Control
12.2.2.4.6.18
MAC Command IDLE
12.2.2.4.6.19
CPSW Network Statistics
12.2.2.4.6.19.1
Rx-only Statistics Descriptions
12.2.2.4.6.19.1.1
Good Rx Frames (Offset = 3A000h)
12.2.2.4.6.19.1.2
Broadcast Rx Frames (Offset = 3A004h)
12.2.2.4.6.19.1.3
Multicast Rx Frames (Offset = 3A008h)
12.2.2.4.6.19.1.4
Pause Rx Frames (Offset = 3A00Ch)
12.2.2.4.6.19.1.5
Rx CRC Errors (Offset = 3A010h)
12.2.2.4.6.19.1.6
Rx Align/Code Errors (Offset = 3A014h)
12.2.2.4.6.19.1.7
Oversize Rx Frames (Offset = 3A018h)
12.2.2.4.6.19.1.8
Rx Jabbers (Offset = 3A01Ch)
12.2.2.4.6.19.1.9
Undersize (Short) Rx Frames (Offset = 3A020h)
12.2.2.4.6.19.1.10
Rx Fragments (Offset = 3A024h)
12.2.2.4.6.19.1.11
RX IPG Error
12.2.2.4.6.19.1.12
ALE Drop (Offset = 3A028h)
12.2.2.4.6.19.1.13
ALE Overrun Drop (Offset = 3A02Ch)
12.2.2.4.6.19.1.14
Rx Octets (Offset = 3A030h)
12.2.2.4.6.19.1.15
Rx Bottom of FIFO Drop (Offset = 3A084h)
12.2.2.4.6.19.1.16
Portmask Drop (Offset = 3A088h)
12.2.2.4.6.19.1.17
Rx Top of FIFO Drop (Offset = 3A08Ch)
12.2.2.4.6.19.1.18
ALE Rate Limit Drop (Offset = 3A090h)
12.2.2.4.6.19.1.19
ALE VLAN Ingress Check Drop (Offset = 3A094h)
2.2.4.6.19.1.19.1
ALE DA=SA Drop (Offset = 3A098h)
2.2.4.6.19.1.19.2
Block Address Drop (Offset = 3A09Ch)
2.2.4.6.19.1.19.3
ALE Secure Drop (Offset = 3A0A0h)
2.2.4.6.19.1.19.4
ALE Authentication Drop (Offset = 3A0A4h)
2.2.4.6.19.1.19.5
ALE Unknown Unicast (Offset = 3A0A8h)
2.2.4.6.19.1.19.6
ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
2.2.4.6.19.1.19.7
ALE Unknown Multicast (Offset = 3A0B0h)
2.2.4.6.19.1.19.8
ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
2.2.4.6.19.1.19.9
ALE Unknown Broadcast (Offset = 3A0B8h)
2.2.4.6.19.1.19.10
ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
2.2.4.6.19.1.19.11
ALE Policer/Classifier Match (Offset = 3A0C0h)
12.2.2.4.6.19.2
ALE Policer Match Red (Offset = 3A0C4h)
12.2.2.4.6.19.3
ALE Policer Match Yellow (Offset = 3A0C8h)
12.2.2.4.6.19.4
IET Receive Assembly Error (Offset = 3A140h)
12.2.2.4.6.19.5
IET Receive Assembly OK (Offset = 3A144h)
12.2.2.4.6.19.6
IET Receive SMD Error (Offset = 3A148h)
12.2.2.4.6.19.7
IET Receive Merge Fragment Count (Offset = 3A14Ch)
12.2.2.4.6.19.8
Tx-only Statistics Descriptions
12.2.2.4.6.19.8.1
Good Tx Frames (Offset = 3A034h)
12.2.2.4.6.19.8.2
Broadcast Tx Frames (Offset = 3A038h)
12.2.2.4.6.19.8.3
Multicast Tx Frames (Offset = 3A03Ch)
12.2.2.4.6.19.8.4
Pause Tx Frames (Offset = 3A040h)
12.2.2.4.6.19.8.5
Deferred Tx Frames (Offset = 3A044h)
12.2.2.4.6.19.8.6
Collisions (Offset = 3A048h)
12.2.2.4.6.19.8.7
Single Collision Tx Frames (Offset = 3A04Ch)
12.2.2.4.6.19.8.8
Multiple Collision Tx Frames (Offset = 3A050h)
12.2.2.4.6.19.8.9
Excessive Collisions (Offset = 3A054h)
12.2.2.4.6.19.8.10
Late Collisions (Offset = 3A058h)
12.2.2.4.6.19.8.11
Carrier Sense Errors (Offset = 3A060h)
12.2.2.4.6.19.8.12
Tx Octets (Offset = 3A064h)
12.2.2.4.6.19.8.13
Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
12.2.2.4.6.19.8.14
Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
12.2.2.4.6.19.8.15
Tx Memory Protect Errors (Offset = 3A17Ch)
12.2.2.4.6.19.8.16
IET Transmit Merge Fragment Count (Offset = 3A14Ch)
12.2.2.4.6.19.8.17
IET Transmit Merge Hold Count (Offset = 3A150h)
12.2.2.4.6.19.9
Rx- and Tx (Shared) Statistics Descriptions
12.2.2.4.6.19.9.1
Rx + Tx 64 Octet Frames (Offset = 3A068h)
12.2.2.4.6.19.9.2
Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
12.2.2.4.6.19.9.3
Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
12.2.2.4.6.19.9.4
Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
12.2.2.4.6.19.9.5
Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
12.2.2.4.6.19.9.6
Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
12.2.2.4.6.19.9.7
Net Octets (Offset = 3A080h)
12.2.2.4.6.19.10
2324
12.2.2.4.7
Common Platform Time Sync (CPTS)
12.2.2.4.7.1
CPSW0 CPTS Integration
12.2.2.4.7.2
CPTS Architecture
12.2.2.4.7.3
CPTS Initialization
12.2.2.4.7.4
32-bit Time Stamp Value
12.2.2.4.7.5
64-bit Time Stamp Value
12.2.2.4.7.6
64-Bit Timestamp Nudge
12.2.2.4.7.7
64-bit Timestamp PPM
12.2.2.4.7.8
Event FIFO
12.2.2.4.7.9
Timestamp Compare Output
12.2.2.4.7.9.1
Non-Toggle Mode: 32-bit
12.2.2.4.7.9.2
Non-Toggle Mode: 64-bit
12.2.2.4.7.9.3
Toggle Mode: 32-bit
12.2.2.4.7.9.4
Toggle Mode: 64-bit
12.2.2.4.7.10
Timestamp Sync Output
12.2.2.4.7.11
Timestamp GENFn Output
12.2.2.4.7.11.1
GENFn Nudge
12.2.2.4.7.11.2
GENFn PPM
12.2.2.4.7.12
Timestamp ESTFn
12.2.2.4.7.13
Time Sync Events
12.2.2.4.7.13.1
Time Stamp Push Event
12.2.2.4.7.13.2
Time Stamp Counter Rollover Event (32-bit mode only)
12.2.2.4.7.13.3
Time Stamp Counter Half-rollover Event (32-bit mode only)
12.2.2.4.7.13.4
Hardware Time Stamp Push Event
12.2.2.4.7.13.5
Ethernet Port Events
12.2.2.4.7.13.5.1
Ethernet Port Receive Event
12.2.2.4.7.13.5.2
Ethernet Port Transmit Event
12.2.2.4.7.13.5.3
2352
12.2.2.4.7.14
Timestamp Compare Event
12.2.2.4.7.14.1
32-Bit Mode
12.2.2.4.7.14.2
64-Bit Mode
12.2.2.4.7.15
Host Transmit Event
12.2.2.4.7.16
CPTS Interrupt Handling
12.2.2.4.8
CPPI Streaming Packet Interface
12.2.2.4.8.1
Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
12.2.2.4.8.2
CPPI Receive Packet Streaming Interface (CPSW Ingress)
12.2.2.4.8.3
CPPI Checksum Offload
12.2.2.4.8.3.1
CPPI Transmit Checksum Offload
12.2.2.4.8.3.1.1
IPV4 UDP
12.2.2.4.8.3.1.2
IPV4 TCP
12.2.2.4.8.3.1.3
IPV6 UDP
12.2.2.4.8.3.1.4
IPV6 TCP
12.2.2.4.8.4
CPPI Receive Checksum Offload
12.2.2.4.8.5
Egress Packet Operations
12.2.2.4.9
MII Management Interface (MDIO)
12.2.2.4.9.1
MDIO Frame Formats
12.2.2.4.9.2
MDIO Functional Description
12.2.2.5
CPSW0 Programming Guide
12.2.2.5.1
Initialization and Configuration of CPSW Subsystem
12.2.2.5.2
Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
12.2.2.5.3
MDIO Software Interface
12.2.2.5.3.1
Initializing the MDIO Module
12.2.2.5.3.2
Writing Data To a PHY Register
12.2.2.5.3.3
Reading Data From a PHY Register
12.2.2.6
CPSW0 Registers
12.2.2.6.1
CPSW0_NUSS Subsystem (SS) Registers
12.2.2.6.2
CPSW0_SGMII Registers
12.2.2.6.3
CPSW0_MDIO Registers
12.2.2.6.4
CPSW0_CPTS Registers
12.2.2.6.5
CPSW0_CONTROL Registers
12.2.2.6.6
CPSW0_CPINT Registers
12.2.2.6.7
CPSW0_RAM Registers
12.2.2.6.8
CPSW0_STAT Registers
12.2.2.6.9
CPSW0_ALE Registers
12.2.2.6.10
CPSW0_PCSR Registers
12.2.2.6.11
CPSW0_ECC Registers
12.2.3
Peripheral Component Interconnect Express (PCIe) Subsystem
12.2.3.1
PCIe Subsystem Overview
12.2.3.1.1
PCIe Subsystem Features
12.2.3.1.2
PCIe Subsystem Not Supported Features
12.2.3.2
PCIe Subsystem Environment
12.2.3.3
PCIe Subsystem Integration
12.2.3.4
PCIe Subsystem Functional Description
12.2.3.4.1
PCIe Subsystem Block Diagram
12.2.3.4.1.1
PCIe Core Module
12.2.3.4.1.2
PCIe PHY Interface
12.2.3.4.1.3
CBA Infrastructure
12.2.3.4.1.4
VBUSM to AXI Bridges
12.2.3.4.1.5
AXI to VBUSM Bridges
12.2.3.4.1.6
VBUSP to APB Bridge
12.2.3.4.1.7
Custom Logic
12.2.3.4.2
PCIe Subsystem Reset Schemes
12.2.3.4.2.1
PCIe Conventional Reset
12.2.3.4.2.2
PCIe Function Level Reset
12.2.3.4.2.3
PCIe Reset Isolation
12.2.3.4.2.3.1
Root Port Reset with Device Not Reset
12.2.3.4.2.3.2
Device Reset with Root Port Not Reset
12.2.3.4.2.3.3
End Point Device Reset with Root Port Not Reset
12.2.3.4.2.3.4
Device Reset with End Point Device Not Reset
12.2.3.4.2.4
PCIe Reset Limitations
12.2.3.4.2.5
PCIe Reset Requirements
12.2.3.4.3
PCIe Subsystem Power Management
12.2.3.4.3.1
CBA Power Management
12.2.3.4.4
PCIe Subsystem Interrupts
12.2.3.4.4.1
Interrupts Aggregation
12.2.3.4.4.2
Interrupt Generation in EP Mode
12.2.3.4.4.2.1
Legacy Interrupt Generation in EP Mode
12.2.3.4.4.2.2
MSI and MSI-X Interrupt Generation
12.2.3.4.4.3
Interrupt Reception in EP Mode
12.2.3.4.4.3.1
PCIe Core Downstream Interrupts
12.2.3.4.4.3.2
PCIe Core Function Level Reset Interrupts
12.2.3.4.4.3.3
PCIe Core Power Management Event Interrupts
12.2.3.4.4.3.4
PCIe Core Hot Reset Request Interrupt
12.2.3.4.4.3.5
PTM Valid Interrupt
12.2.3.4.4.4
Interrupt Generation in RP Mode
12.2.3.4.4.5
Interrupt Reception in RP Mode
12.2.3.4.4.5.1
PCIe Legacy Interrupt Reception in RP Mode
12.2.3.4.4.5.2
MSI/MSI-X Interrupt Reception in RP Mode
12.2.3.4.4.5.3
Advanced Error Reporting Interrupt
12.2.3.4.4.6
Common Interrupt Reception in RP and EP Modes
12.2.3.4.4.6.1
PCIe Local Interrupt
12.2.3.4.4.6.2
PHY Interrupt
12.2.3.4.4.6.3
Link down Interrupt
12.2.3.4.4.6.4
Transaction Error Interrupts
12.2.3.4.4.6.5
Power Management Event Interrupt
12.2.3.4.4.6.6
Active Internal Diagnostics Interrupts
12.2.3.4.4.7
ECC Aggregator Interrupts
12.2.3.4.4.8
CPTS Interrupt
12.2.3.4.5
PCIe Subsystem DMA Support
12.2.3.4.5.1
PCIe DMA Support in RP Mode
12.2.3.4.5.2
PCIe DMA Support in EP Mode
12.2.3.4.6
PCIe Subsystem Transactions
12.2.3.4.6.1
PCIe Supported Transactions
12.2.3.4.6.2
PCIe Transaction Limitations
12.2.3.4.7
PCIe Subsystem Address Translation
12.2.3.4.7.1
PCIe Inbound Address Translation
12.2.3.4.7.1.1
Root Port Inbound PCIe to AXI Address Translation
12.2.3.4.7.1.2
End Point Inbound PCIe to AXI Address Translation
12.2.3.4.7.2
PCIe Outbound Address Translation
12.2.3.4.7.2.1
PCIe Outbound Address Translation Bypass
12.2.3.4.8
PCIe Subsystem Virtualization Support
12.2.3.4.8.1
End Point SR-IOV Support
12.2.3.4.8.2
Root Port ATS Support
12.2.3.4.8.3
VirtID Mapping
12.2.3.4.9
PCIe Subsystem Quality-of-Service (QoS)
12.2.3.4.10
PCIe Subsystem Precision Time Measurement (PTM)
12.2.3.4.11
PCIe Subsystem Loopback
12.2.3.4.11.1
PCIe PIPE Loopback
12.2.3.4.11.1.1
PIPE Loopback Master Mode
12.2.3.4.11.1.2
PIPE Loopback Slave Mode
12.2.3.4.12
PCIe Subsystem Error Handling
12.2.3.4.12.1
PCIe AXI to/from VBUSM Bus Error Mapping
12.2.3.4.13
PCIe Subsystem Internal Diagnostics Features
12.2.3.4.13.1
PCIe Parity
12.2.3.4.13.2
ECC Aggregators
12.2.3.4.13.3
RAM ECC Inversion
12.2.3.4.14
LTSSM State Encoding
12.2.3.5
PCIe Subsystem Registers
12.2.3.5.1
PCIE_CORE_EP_PF Registers
12.2.3.5.2
PCIE_CORE_EP_VF Registers
12.2.3.5.3
PCIE_CORE_RP Registers
12.2.3.5.4
PCIE_CORE_LM Registers
12.2.3.5.5
PCIE_CORE_AXI Registers
12.2.3.5.6
PCIE_INTD Registers
12.2.3.5.7
PCIE_VMAP Registers
12.2.3.5.8
PCIE_CPTS Registers
12.2.3.5.9
PCIE_USER_CFG Registers
12.2.3.5.10
PCIE_ECC_AGGR0 Registers
12.2.3.5.11
PCIE_ECC_AGGR1 Registers
12.2.3.5.12
PCIE_DAT0 Registers
12.2.3.5.13
PCIE_DAT1 Registers
12.2.4
Universal Serial Bus (USB) Subsystem
12.2.4.1
USB Overview
12.2.4.1.1
USB Features
12.2.4.1.2
USB Not Supported Features
12.2.4.1.3
USB Terminology
12.2.4.2
USB Environment
12.2.4.3
USB Integration
12.2.4.4
USB Functional Description
12.2.4.4.1
USB Type-C Connector Support
12.2.4.4.2
USB Controller Reset
12.2.4.4.3
Overcurrent Detection
12.2.4.4.4
Top-Level Initialization Sequence
12.2.4.5
USB Registers
12.2.4.5.1
USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
12.2.4.5.2
USB_ECC_AGGR_CFG Registers
12.2.4.5.3
USB_RAMS_INJ_CFG Registers
12.2.5
Serializer/Deserializer (SerDes)
12.2.5.1
SerDes Overview
12.2.5.1.1
SerDes Features
12.2.5.1.2
Industry Standards Compatibility
12.2.5.2
SerDes Environment
12.2.5.2.1
SerDes I/Os
12.2.5.3
SerDes Integration
12.2.5.3.1
WIZ Settings
12.2.5.3.1.1
Interface Selection
12.2.5.3.1.2
Reference Clock Distribution
12.2.5.3.1.3
Internal Reference Clock Selection
12.2.5.4
SerDes Functional Description
12.2.5.4.1
SerDes Block Diagram
12.2.5.4.2
SerDes Programming Guide
12.3
Memory Interfaces
12.3.1
Flash Subsystem (FSS)
12.3.1.1
FSS Overview
12.3.1.1.1
FSS Features
12.3.1.1.2
FSS Not Supported Features
12.3.1.2
FSS Environment
12.3.1.2.1
FSS Typical Application
12.3.1.3
FSS Integration
12.3.1.3.1
FSS Integration in MCU Domain
12.3.1.4
FSS Functional Description
12.3.1.4.1
FSS Block Diagram
12.3.1.4.2
FSS ECC Support
12.3.1.4.2.1
FSS ECC Calculation
12.3.1.4.3
FSS Modes of Operation
12.3.1.4.4
FSS Regions
12.3.1.4.4.1
FSS Regions Boot Size Configuration
12.3.1.4.5
FSS Memory Regions
12.3.1.5
FSS Programming Guide
12.3.1.5.1
FSS Initialization Sequence
12.3.1.5.2
FSS Real-Time Operation
12.3.1.5.3
FSS Power Up/Down Sequence
12.3.1.6
FSS Registers
12.3.2
Octal Serial Peripheral Interface (OSPI)
12.3.2.1
OSPI Overview
12.3.2.1.1
OSPI Features
12.3.2.1.2
OSPI Not Supported Features
12.3.2.2
OSPI Environment
12.3.2.3
OSPI Integration
12.3.2.3.1
OSPI Integration in MCU Domain
12.3.2.4
OSPI Functional Description
12.3.2.4.1
OSPI Block Diagram
12.3.2.4.1.1
Data Target Interface
12.3.2.4.1.2
Configuration Target Interface
12.3.2.4.1.3
OSPI Clock Domains
12.3.2.4.2
OSPI Modes
12.3.2.4.2.1
Read Data Capture
12.3.2.4.2.1.1
Mechanisms of Data Capturing
12.3.2.4.2.1.2
Data Capturing Mechanism Using Taps
12.3.2.4.2.1.3
Data Capturing Mechanism Using PHY Module
12.3.2.4.2.2
External Pull Down on DQS
12.3.2.4.3
OSPI Power Management
12.3.2.4.4
Auto HW Polling
12.3.2.4.5
Flash Reset
12.3.2.4.6
OSPI Memory Regions
12.3.2.4.7
OSPI Interrupt Requests
12.3.2.4.8
OSPI Data Interface
12.3.2.4.8.1
Data Interface Address Remapping
12.3.2.4.8.2
Write Protection
12.3.2.4.8.3
Access Forwarding
12.3.2.4.9
OSPI Direct Access Controller (DAC)
12.3.2.4.10
OSPI Indirect Access Controller (INDAC)
12.3.2.4.10.1
Indirect Read Controller
12.3.2.4.10.1.1
Indirect Read Transfer Process
12.3.2.4.10.2
Indirect Write Controller
12.3.2.4.10.2.1
Indirect Write Transfer Process
12.3.2.4.10.3
Indirect Access Queuing
12.3.2.4.10.4
Consecutive Writes and Reads Using Indirect Transfers
12.3.2.4.10.5
Accessing the SRAM
12.3.2.4.11
OSPI Software-Triggered Instruction Generator (STIG)
12.3.2.4.11.1
Servicing a STIG Request
12.3.2.4.11.2
2576
12.3.2.4.12
OSPI Arbitration Between Direct / Indirect Access Controller and STIG
12.3.2.4.13
OSPI Command Translation
12.3.2.4.14
Selecting the Flash Instruction Type
12.3.2.4.15
OSPI Data Integrity
12.3.2.4.16
OSPI PHY Module
12.3.2.4.16.1
PHY Pipeline Mode
12.3.2.4.16.2
Read Data Capturing by the PHY Module
12.3.2.5
OSPI Programming Guide
12.3.2.5.1
Configuring the OSPI Controller for Use After Reset
12.3.2.5.2
Configuring the OSPI Controller for Optimal Use
12.3.2.5.3
Using the Flash Command Control Register (STIG Operation)
12.3.2.5.4
Using SPI Legacy Mode
12.3.2.5.5
Entering XIP Mode from POR
12.3.2.5.6
Entering XIP Mode Otherwise
12.3.2.5.7
Exiting XIP Mode
12.3.2.6
OSPI Registers
12.3.3
HyperBus Interface
12.3.3.1
HyperBus Overview
12.3.3.1.1
HyperBus Features
12.3.3.1.2
HyperBus Not Supported Features
12.3.3.2
HyperBus Environment
12.3.3.3
HyperBus Integration
12.3.3.3.1
HyperBus Integration in MCU Domain
12.3.3.4
HyperBus Functional Description
12.3.3.4.1
HyperBus Interrupts
12.3.3.4.2
HyperBus ECC Support
12.3.3.4.2.1
ECC Aggregator
12.3.3.4.3
HyperBus Internal FIFOs
12.3.3.4.4
HyperBus Data Regions
12.3.3.4.5
HyperBus True Continuous Read (TCR) Mode
12.3.3.5
HyperBus Programming Guide
12.3.3.5.1
HyperBus Initialization Sequence
12.3.3.5.1.1
HyperFlash Access
12.3.3.5.1.2
HyperRAM Access
12.3.3.5.2
HyperBus Real-time Operating Requirements
12.3.3.5.3
HyperBus Power Up/Down Sequence
12.3.3.6
HyperBus Registers
12.3.4
General-Purpose Memory Controller (GPMC)
12.3.4.1
GPMC Overview
12.3.4.1.1
GPMC Features
12.3.4.1.2
GPMC Not Supported Features
12.3.4.2
GPMC Environment
12.3.4.2.1
GPMC Modes
12.3.4.2.2
GPMC I/O Signals
12.3.4.3
GPMC Integration
12.3.4.3.1
GPMC Integration in MAIN Domain
12.3.4.4
GPMC Functional Description
12.3.4.4.1
GPMC Block Diagram
12.3.4.4.2
GPMC Clock Configuration
12.3.4.4.3
GPMC Power Management
12.3.4.4.4
GPMC Interrupt Requests
12.3.4.4.5
GPMC Interconnect Port Interface
12.3.4.4.6
GPMC Address and Data Bus
12.3.4.4.6.1
GPMC I/O Configuration Setting
12.3.4.4.7
GPMC Address Decoder and Chip-Select Configuration
12.3.4.4.7.1
Chip-Select Base Address and Region Size
12.3.4.4.7.2
Access Protocol
12.3.4.4.7.2.1
Supported Devices
12.3.4.4.7.2.2
Access Size Adaptation and Device Width
12.3.4.4.7.2.3
Address/Data-Multiplexing Interface
12.3.4.4.7.3
External Signals
12.3.4.4.7.3.1
WAIT Pin Monitoring Control
12.3.4.4.7.3.1.1
Wait Monitoring During Asynchronous Read Access
12.3.4.4.7.3.1.2
Wait Monitoring During Asynchronous Write Access
12.3.4.4.7.3.1.3
Wait Monitoring During Synchronous Read Access
12.3.4.4.7.3.1.4
Wait Monitoring During Synchronous Write Access
12.3.4.4.7.3.1.5
Wait With NAND Device
12.3.4.4.7.3.1.6
Idle Cycle Control Between Successive Accesses
3.4.4.7.3.1.6.1
Bus Turnaround (BUSTURNAROUND)
3.4.4.7.3.1.6.2
Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
3.4.4.7.3.1.6.3
Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
12.3.4.4.7.3.1.7
Slow Device Support (TIMEPARAGRANULARITY Parameter)
12.3.4.4.7.3.2
DIR Pin
12.3.4.4.7.3.3
Reset
12.3.4.4.7.3.4
Write Protect Signal (nWP)
12.3.4.4.7.3.5
Byte Enable (nBE1/nBE0)
12.3.4.4.7.4
Error Handling
12.3.4.4.8
GPMC Timing Setting
12.3.4.4.8.1
Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
12.3.4.4.8.2
nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
12.3.4.4.8.3
nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
12.3.4.4.8.4
nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
12.3.4.4.8.5
nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
12.3.4.4.8.6
GPMC_CLKOUT
12.3.4.4.8.7
GPMC Output Clock and Control Signals Setup and Hold
12.3.4.4.8.8
Access Time (RDACCESSTIME / WRACCESSTIME)
12.3.4.4.8.8.1
Access Time on Read Access
12.3.4.4.8.8.2
Access Time on Write Access
12.3.4.4.8.9
Page Burst Access Time (PAGEBURSTACCESSTIME)
12.3.4.4.8.9.1
Page Burst Access Time on Read Access
12.3.4.4.8.9.2
Page Burst Access Time on Write Access
12.3.4.4.8.10
Bus Keeping Support
12.3.4.4.9
GPMC NOR Access Description
12.3.4.4.9.1
Asynchronous Access Description
12.3.4.4.9.1.1
Access on Address/Data Multiplexed Devices
12.3.4.4.9.1.1.1
Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
12.3.4.4.9.1.1.2
Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
12.3.4.4.9.1.1.3
Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
12.3.4.4.9.1.2
Access on Address/Address/Data-Multiplexed Devices
12.3.4.4.9.1.2.1
Asynchronous Single Read Operation on an AAD-Multiplexed Device
12.3.4.4.9.1.2.2
Asynchronous Single-Write Operation on an AAD-Multiplexed Device
12.3.4.4.9.1.2.3
Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
12.3.4.4.9.2
Synchronous Access Description
12.3.4.4.9.2.1
Synchronous Single Read
12.3.4.4.9.2.2
Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
12.3.4.4.9.2.3
Synchronous Single Write
12.3.4.4.9.2.4
Synchronous Multiple (Burst) Write
12.3.4.4.9.3
Asynchronous and Synchronous Accesses in non-multiplexed Mode
12.3.4.4.9.3.1
Asynchronous Single-Read Operation on non-multiplexed Device
12.3.4.4.9.3.2
Asynchronous Single-Write Operation on non-multiplexed Device
12.3.4.4.9.3.3
Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
12.3.4.4.9.3.4
Synchronous Operations on a non-multiplexed Device
12.3.4.4.9.4
Page and Burst Support
12.3.4.4.9.5
System Burst vs External Device Burst Support
12.3.4.4.10
GPMC pSRAM Access Specificities
12.3.4.4.11
GPMC NAND Access Description
12.3.4.4.11.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
12.3.4.4.11.1.1
Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
12.3.4.4.11.1.2
NAND Device Command and Address Phase Control
12.3.4.4.11.1.3
Command Latch Cycle
12.3.4.4.11.1.4
Address Latch Cycle
12.3.4.4.11.1.5
NAND Device Data Read and Write Phase Control in Stream Mode
12.3.4.4.11.1.6
NAND Device General Chip-Select Timing Control Requirement
12.3.4.4.11.1.7
Read and Write Access Size Adaptation
12.3.4.4.11.1.7.1
8-Bit-Wide NAND Device
12.3.4.4.11.1.7.2
16-Bit-Wide NAND Device
12.3.4.4.11.2
NAND Device-Ready Pin
12.3.4.4.11.2.1
Ready Pin Monitored by Software Polling
12.3.4.4.11.2.2
Ready Pin Monitored by Hardware Interrupt
12.3.4.4.11.3
ECC Calculator
12.3.4.4.11.3.1
Hamming Code
12.3.4.4.11.3.1.1
ECC Result Register and ECC Computation Accumulation Size
12.3.4.4.11.3.1.2
ECC Enabling
12.3.4.4.11.3.1.3
ECC Computation
12.3.4.4.11.3.1.4
ECC Comparison and Correction
12.3.4.4.11.3.1.5
ECC Calculation Based on 8-Bit Word
12.3.4.4.11.3.1.6
ECC Calculation Based on 16-Bit Word
12.3.4.4.11.3.2
BCH Code
12.3.4.4.11.3.2.1
Requirements
12.3.4.4.11.3.2.2
Memory Mapping of BCH Codeword
3.4.4.11.3.2.2.1
Memory Mapping of Data Message
3.4.4.11.3.2.2.2
Memory-Mapping of the ECC
3.4.4.11.3.2.2.3
Wrapping Modes
4.4.11.3.2.2.3.1
Manual Mode (0x0)
4.4.11.3.2.2.3.2
Mode 0x1
4.4.11.3.2.2.3.3
Mode 0xA (10)
4.4.11.3.2.2.3.4
Mode 0x2
4.4.11.3.2.2.3.5
Mode 0x3
4.4.11.3.2.2.3.6
Mode 0x7
4.4.11.3.2.2.3.7
Mode 0x8
4.4.11.3.2.2.3.8
Mode 0x4
4.4.11.3.2.2.3.9
Mode 0x9
4.4.11.3.2.2.3.10
Mode 0x5
4.4.11.3.2.2.3.11
Mode 0xB (11)
4.4.11.3.2.2.3.12
Mode 0x6
12.3.4.4.11.3.2.3
Supported NAND Page Mappings and ECC Schemes
3.4.4.11.3.2.3.1
Per-Sector Spare Mappings
3.4.4.11.3.2.3.2
Pooled Spare Mapping
3.4.4.11.3.2.3.3
Per-Sector Spare Mapping, with ECC Separated at the End of the Page
12.3.4.4.11.4
Prefetch and Write-Posting Engine
12.3.4.4.11.4.1
General Facts About the Engine Configuration
12.3.4.4.11.4.2
Prefetch Mode
12.3.4.4.11.4.3
FIFO Control in Prefetch Mode
12.3.4.4.11.4.4
Write-Posting Mode
12.3.4.4.11.4.5
FIFO Control in Write-Posting Mode
12.3.4.4.11.4.6
Optimizing NAND Access Using the Prefetch and Write-Posting Engine
12.3.4.4.11.4.7
Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
12.3.4.4.12
GPMC Use Cases and Tips
12.3.4.4.12.1
How to Set GPMC Timing Parameters for Typical Accesses
12.3.4.4.12.1.1
External Memory Attached to the GPMC Module
12.3.4.4.12.1.2
Typical GPMC Setup
12.3.4.4.12.1.2.1
GPMC Configuration for Synchronous Burst Read Access
12.3.4.4.12.1.2.2
GPMC Configuration for Asynchronous Read Access
12.3.4.4.12.1.2.3
GPMC Configuration for Asynchronous Single Write Access
12.3.4.4.12.2
How to Choose a Suitable Memory to Use With the GPMC
12.3.4.4.12.2.1
Supported Memories or Devices
12.3.4.4.12.2.1.1
Memory Pin Multiplexing
12.3.4.4.12.2.1.2
NAND Interface Protocol
12.3.4.4.12.2.1.3
NOR Interface Protocol
12.3.4.4.12.2.1.4
Other Technologies
12.3.4.5
GPMC Basic Programming Model
12.3.4.5.1
GPMC High-Level Programming Model Overview
12.3.4.5.2
GPMC Initialization
12.3.4.5.3
GPMC Configuration in NOR Mode
12.3.4.5.4
GPMC Configuration in NAND Mode
12.3.4.5.5
Set Memory Access
12.3.4.5.6
GPMC Timing Parameters
12.3.4.5.6.1
GPMC Timing Parameters Formulas
12.3.4.5.6.1.1
NAND Flash Interface Timing Parameters Formulas
12.3.4.5.6.1.2
Synchronous NOR Flash Timing Parameters Formulas
12.3.4.5.6.1.3
Asynchronous NOR Flash Timing Parameters Formulas
12.3.4.6
GPMC Registers
12.3.5
Error Location Module (ELM)
12.3.5.1
ELM Overview
12.3.5.1.1
ELM Features
12.3.5.1.2
ELM Not Supported Features
12.3.5.2
ELM Integration
12.3.5.2.1
ELM Integration in MAIN Domain
12.3.5.3
ELM Functional Description
12.3.5.3.1
ELM Software Reset
12.3.5.3.2
ELM Power Management
12.3.5.3.3
ELM Interrupt Requests
12.3.5.3.4
ELM Processing Initialization
12.3.5.3.5
ELM Processing Sequence
12.3.5.3.6
ELM Processing Completion
12.3.5.4
ELM Basic Programming Model
12.3.5.4.1
ELM Low-Level Programming Model
12.3.5.4.1.1
Processing Initialization
12.3.5.4.1.2
Read Results
12.3.5.4.1.3
2786
12.3.5.4.2
Use Case: ELM Used in Continuous Mode
12.3.5.4.3
Use Case: ELM Used in Page Mode
12.3.5.5
ELM Registers
12.3.6
Multi-Media Card Secure Digital (MMCSD) Interface
12.3.6.1
MMCSD Overview
12.3.6.1.1
MMCSD Features
12.3.6.1.2
MMCSD Not Supported Features
12.3.6.2
MMCSD Environment
12.3.6.2.1
Protocol and Data Format
12.3.6.2.1.1
Protocol
12.3.6.2.1.2
Data Format
12.3.6.2.1.2.1
Coding Scheme for Command Token
12.3.6.2.1.2.2
Coding Scheme for Response Token
12.3.6.2.1.2.3
Coding Scheme for Data Token
12.3.6.3
MMCSD Integration
12.3.6.3.1
MMCSD Integration in MAIN Domain
12.3.6.4
MMCSD Functional Description
12.3.6.4.1
Block Diagram
12.3.6.4.2
Memory Regions
12.3.6.4.3
Interrupt Requests
12.3.6.4.4
ECC Support
12.3.6.4.4.1
ECC Aggregator
12.3.6.4.5
Advanced DMA
12.3.6.4.6
eMMC PHY BIST
12.3.6.4.6.1
BIST Overview
12.3.6.4.6.2
BIST Modes
12.3.6.4.6.2.1
DS Mode
12.3.6.4.6.2.2
HS Mode with TXDLY using DLL
12.3.6.4.6.2.3
HS Mode with TXDLY using Delay Chain
12.3.6.4.6.2.4
DDR50 Mode with TXDLY using DLL
12.3.6.4.6.2.5
DDR50 Mode with TXDLY using Delay Chain
12.3.6.4.6.2.6
HS200 Mode with TX/RXDLY using DLL
12.3.6.4.6.2.7
HS200 Mode with TX/RXDLY using Delay Chain
12.3.6.4.6.2.8
HS400 Mode
12.3.6.4.6.3
BIST Functionality
12.3.6.4.6.4
Signal Interface
12.3.6.4.6.5
Programming Flow
12.3.6.4.6.5.1
DS Mode
12.3.6.4.6.5.1.1
Configuration
12.3.6.4.6.5.1.2
BIST Programming
12.3.6.4.6.5.2
HS Mode with DLY_CHAIN
12.3.6.4.6.5.2.1
Configuration
12.3.6.4.6.5.2.2
BIST Programming
12.3.6.4.6.5.3
HS Mode with DLL
12.3.6.4.6.5.3.1
Configuration
12.3.6.4.6.5.3.2
BIST Programming
12.3.6.4.6.5.4
DDR52 Mode with DLY_CHAIN
12.3.6.4.6.5.4.1
Configuration
12.3.6.4.6.5.4.2
BIST Programming
12.3.6.4.6.5.5
DDR52 Mode with DLL
12.3.6.4.6.5.5.1
Configuration
12.3.6.4.6.5.5.2
BIST Programming
12.3.6.4.6.5.6
HS200 Mode with DLY_CHAIN
12.3.6.4.6.5.6.1
Configuration
12.3.6.4.6.5.6.2
BIST Programming
12.3.6.4.6.5.7
HS200 Mode with DLL
12.3.6.4.6.5.7.1
Configuration
12.3.6.4.6.5.7.2
BIST Programming
12.3.6.4.6.5.8
HS400 Mode with DLL
12.3.6.4.6.5.8.1
Configuration
12.3.6.4.6.5.8.2
BIST Programming
12.3.6.4.6.6
HS200 BIST Result Check Procedure
12.3.6.5
MMCSD Programming Guide
12.3.6.5.1
Sequences
12.3.6.5.1.1
SD Card Detection
12.3.6.5.1.2
SD Clock Control
12.3.6.5.1.2.1
Internal Clock Setup Sequence
12.3.6.5.1.2.2
SD Clock Supply and Stop Sequence
12.3.6.5.1.2.3
SD Clock Frequency Change Sequence
12.3.6.5.1.3
SD Bus Power Control
12.3.6.5.1.4
Changing Bus Width
12.3.6.5.1.5
Timeout Setting on DAT Line
12.3.6.5.1.6
Card Initialization and Identification (for SD I/F)
12.3.6.5.1.6.1
Signal Voltage Switch Procedure (for UHS-I)
12.3.6.5.1.7
SD Transaction Generation
12.3.6.5.1.7.1
Transaction Control without Data Transfer Using DAT Line
12.3.6.5.1.7.1.1
The Sequence to Issue a SD Command
12.3.6.5.1.7.1.2
The Sequence to Finalize a Command
12.3.6.5.1.7.1.3
2865
12.3.6.5.1.7.2
Transaction Control with Data Transfer Using DAT Line
12.3.6.5.1.7.2.1
Not using DMA
12.3.6.5.1.7.2.2
Using SDMA
12.3.6.5.1.7.2.3
Using ADMA
12.3.6.5.1.8
Abort Transaction
12.3.6.5.1.8.1
Asynchronous Abort
12.3.6.5.1.8.2
Synchronous Abort
12.3.6.5.1.9
Changing Bus Speed Mode
12.3.6.5.1.10
Error Recovery
12.3.6.5.1.10.1
Error Interrupt Recovery
12.3.6.5.1.10.2
Auto CMD12 Error Recovery
12.3.6.5.1.11
Wakeup Control (Optional)
12.3.6.5.1.12
Suspend/Resume (Optional, Not Supported from Version 4.00)
12.3.6.5.1.12.1
Suspend Sequence
12.3.6.5.1.12.2
Resume Sequence
12.3.6.5.1.12.3
Stop At Block Gap/Continue Timing for Read Transaction
12.3.6.5.1.12.4
Stop At Block Gap/Continue Timing for Write Transaction
12.3.6.5.2
Driver Flow Sequence
12.3.6.5.2.1
Host Controller Setup and Card Detection
12.3.6.5.2.1.1
Host Controller Setup Sequence
12.3.6.5.2.1.2
Card Interface Detection Sequence
12.3.6.5.2.2
Boot Operation
12.3.6.5.2.2.1
Normal Boot Operation: (For Legacy eMMC 5.0)
12.3.6.5.2.2.2
Alternate Boot Operation (For Legacy eMMC 5.0):
12.3.6.5.2.2.3
Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
12.3.6.5.2.3
Retuning procedure (For Legacy Interface)
12.3.6.5.2.3.1
Sampling Clock Tuning
12.3.6.5.2.3.2
Tuning Modes
12.3.6.5.2.3.3
Re-Tuning Mode 2
12.3.6.5.2.4
Command Queuing Driver Flow Sequence
12.3.6.5.2.4.1
Command Queuing Initialization Sequence
12.3.6.5.2.4.2
Task Issuance Sequence
12.3.6.5.2.4.3
Task Execution and Completion Sequence
12.3.6.5.2.4.4
Task Discard and Clear Sequence
12.3.6.5.2.4.5
Error Detect and Recovery when CQ is enabled
12.3.6.6
MMCSD Registers
12.3.6.6.1
MMCSD0 Subsystem Registers
12.3.6.6.2
MMCSD0 RX RAM ECC Aggregator Registers
12.3.6.6.3
MMCSD0 TX RAM ECC Aggregator Registers
12.3.6.6.4
MMCSD0 Host Controller Registers
12.3.6.6.5
MMCSD1 Subsystem Registers
12.3.6.6.6
MMCSD1 RX RAM ECC Aggregator Registers
12.3.6.6.7
MMCSD1 TX RAM ECC Aggregator Registers
12.3.6.6.8
MMCSD1 Host Controller Registers
12.4
Industrial and Control Interfaces
12.4.1
Enhanced Capture (ECAP) Module
12.4.1.1
ECAP Overview
12.4.1.1.1
ECAP Features
12.4.1.2
ECAP Environment
12.4.1.2.1
ECAP I/O Interface
12.4.1.3
ECAP Integration
12.4.1.3.1
Daisy-Chain Connectivity between ECAP Modules
12.4.1.4
ECAP Functional Description
12.4.1.4.1
Capture and APWM Operating Modes
12.4.1.4.1.1
ECAP Capture Mode Description
12.4.1.4.1.1.1
ECAP Event Prescaler
12.4.1.4.1.1.2
ECAP Edge Polarity Select and Qualifier
12.4.1.4.1.1.3
ECAP Continuous/One-Shot Control
12.4.1.4.1.1.4
ECAP 32-Bit Counter and Phase Control
12.4.1.4.1.1.5
CAP1-CAP4 Registers
12.4.1.4.1.1.6
ECAP Interrupt Control
12.4.1.4.1.1.7
ECAP Shadow Load and Lockout Control
12.4.1.4.1.2
ECAP APWM Mode Operation
12.4.1.4.2
Summary of ECAP Functional Registers
12.4.1.5
ECAP Use Cases
12.4.1.5.1
Absolute Time-Stamp Operation Rising Edge Trigger Example
12.4.1.5.1.1
Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
12.4.1.5.2
Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
12.4.1.5.2.1
Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
12.4.1.5.3
Time Difference (Delta) Operation Rising Edge Trigger Example
12.4.1.5.3.1
Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
12.4.1.5.4
Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
12.4.1.5.4.1
Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
12.4.1.5.5
Application of the APWM Mode
12.4.1.5.5.1
Simple PWM Generation (Independent Channel/s) Example
12.4.1.5.5.1.1
Code Snippet for APWM Mode
12.4.1.5.5.2
Multichannel PWM Generation with Synchronization Example
12.4.1.5.5.2.1
Code Snippet for Multichannel PWM Generation with Synchronization
12.4.1.5.5.3
Multichannel PWM Generation with Phase Control Example
12.4.1.5.5.3.1
Code Snippet for Multichannel PWM Generation with Phase Control
12.4.1.6
ECAP Registers
12.4.2
Enhanced Pulse Width Modulation (EPWM) Module
12.4.2.1
EPWM Overview
12.4.2.1.1
EPWM Features
12.4.2.1.2
EPWM Not Supported Features
12.4.2.1.3
2951
12.4.2.2
EPWM Environment
12.4.2.2.1
EPWM I/O Interface
12.4.2.3
EPWM Integration
12.4.2.3.1
Device Specific EPWM Features
12.4.2.3.2
Daisy-Chain Connectivity between EPWM Modules
12.4.2.3.3
ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
12.4.2.3.4
EPWM Modules Time Base Clock Gating
12.4.2.4
EPWM Functional Description
12.4.2.4.1
EPWM Submodule Features
12.4.2.4.1.1
Constant Definitions Used in the EPWM Code Examples
12.4.2.4.2
EPWM Time-Base (TB) Submodule
12.4.2.4.2.1
Overview
12.4.2.4.2.2
2964
12.4.2.4.2.3
Controlling and Monitoring the EPWM Time-Base Submodule
12.4.2.4.2.4
Calculating PWM Period and Frequency
12.4.2.4.2.4.1
EPWM Time-Base Period Shadow Register
12.4.2.4.2.4.2
EPWM Time-Base Counter Synchronization
12.4.2.4.2.5
Phase Locking the Time-Base Clocks of Multiple EPWM Modules
12.4.2.4.2.6
EPWM Time-Base Counter Modes and Timing Waveforms
12.4.2.4.3
EPWM Counter-Compare (CC) Submodule
12.4.2.4.3.1
Overview
12.4.2.4.3.2
Controlling and Monitoring the EPWM Counter-Compare Submodule
12.4.2.4.3.3
Operational Highlights for the EPWM Counter-Compare Submodule
12.4.2.4.3.4
EPWM Counter-Compare Submodule Timing Waveforms
12.4.2.4.4
EPWM Action-Qualifier (AQ) Submodule
12.4.2.4.4.1
Overview
12.4.2.4.4.2
Controlling and Monitoring the EPWM Action-Qualifier Submodule
12.4.2.4.4.3
EPWM Action-Qualifier Event Priority
12.4.2.4.4.4
Waveforms for Common EPWM Configurations
12.4.2.4.5
EPWM Dead-Band Generator (DB) Submodule
12.4.2.4.5.1
Overview
12.4.2.4.5.2
Controlling and Monitoring the EPWM Dead-Band Submodule
12.4.2.4.5.3
Operational Highlights for the EPWM Dead-Band Generator Submodule
12.4.2.4.6
EPWM-Chopper (PC) Submodule
12.4.2.4.6.1
Overview
12.4.2.4.6.2
2987
12.4.2.4.6.3
Controlling the EPWM-Chopper Submodule
12.4.2.4.6.4
Operational Highlights for the EPWM-Chopper Submodule
12.4.2.4.6.5
EPWM-Chopper Waveforms
12.4.2.4.6.5.1
EPWM-Chopper One-Shot Pulse
12.4.2.4.6.5.2
EPWM-Chopper Duty Cycle Control
12.4.2.4.7
EPWM Trip-Zone (TZ) Submodule
12.4.2.4.7.1
Overview
12.4.2.4.7.2
Controlling and Monitoring the EPWM Trip-Zone Submodule
12.4.2.4.7.3
Operational Highlights for the EPWM Trip-Zone Submodule
12.4.2.4.7.4
Generating EPWM Trip-Event Interrupts
12.4.2.4.8
EPWM Event-Trigger (ET) Submodule
12.4.2.4.8.1
Overview
12.4.2.4.8.2
Controlling and Monitoring the EPWM Event-Trigger Submodule
12.4.2.4.8.3
Operational Overview of the EPWM Event-Trigger Submodule
12.4.2.4.8.4
3002
12.4.2.4.9
EPWM High Resolution (HRPWM) Submodule
12.4.2.4.9.1
Overview
12.4.2.4.9.2
Architecture of the High-Resolution PWM Submodule
12.4.2.4.9.3
Controlling and Monitoring the High-Resolution PWM Submodule
12.4.2.4.9.4
Configuring the High-Resolution PWM Submodule
12.4.2.4.9.5
Operational Highlights for the High-Resolution PWM Submodule
12.4.2.4.9.5.1
HRPWM Edge Positioning
12.4.2.4.9.5.2
HRPWM Scaling Considerations
12.4.2.4.9.5.3
HRPWM Duty Cycle Range Limitation
12.4.2.4.10
EPWM / HRPWM Functional Register Groups
12.4.2.4.11
Proper EPWM Interrupt Initialization Procedure
12.4.2.5
EPWM Registers
12.4.3
Enhanced Quadrature Encoder Pulse (EQEP) Module
12.4.3.1
EQEP Overview
12.4.3.1.1
EQEP Features
12.4.3.1.2
EQEP Not Supported Features
12.4.3.2
EQEP Environment
12.4.3.2.1
EQEP I/O Interface
12.4.3.3
EQEP Integration
12.4.3.3.1
Device Specific EQEP Features
12.4.3.4
EQEP Functional Description
12.4.3.4.1
EQEP Inputs
12.4.3.4.2
EQEP Quadrature Decoder Unit (QDU)
12.4.3.4.2.1
EQEP Position Counter Input Modes
12.4.3.4.2.1.1
Quadrature Count Mode
12.4.3.4.2.1.2
EQEP Direction-count Mode
12.4.3.4.2.1.3
EQEP Up-Count Mode
12.4.3.4.2.1.4
EQEP Down-Count Mode
12.4.3.4.2.2
EQEP Input Polarity Selection
12.4.3.4.2.3
EQEP Position-Compare Sync Output
12.4.3.4.3
EQEP Position Counter and Control Unit (PCCU)
12.4.3.4.3.1
EQEP Position Counter Operating Modes
12.4.3.4.3.1.1
EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
12.4.3.4.3.1.2
EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
12.4.3.4.3.1.3
Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
12.4.3.4.3.1.4
Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
12.4.3.4.3.2
EQEP Position Counter Latch
12.4.3.4.3.2.1
Index Event Latch
12.4.3.4.3.2.2
EQEP Strobe Event Latch
12.4.3.4.3.3
EQEP Position Counter Initialization
12.4.3.4.3.4
EQEP Position-Compare Unit
12.4.3.4.4
EQEP Edge Capture Unit
12.4.3.4.5
EQEP Watchdog
12.4.3.4.6
Unit Timer Base
12.4.3.4.7
EQEP Interrupt Structure
12.4.3.4.8
Summary of EQEP Functional Registers
12.4.3.5
EQEP Registers
12.4.4
Controller Area Network (MCAN)
12.4.4.1
MCAN Overview
12.4.4.1.1
MCAN Features
12.4.4.1.2
MCAN Not Supported Features
12.4.4.2
MCAN Environment
12.4.4.2.1
CAN Network Basics
12.4.4.3
MCAN Integration
12.4.4.3.1
MCAN Integration in MCU Domain
12.4.4.3.2
MCAN Integration in MAIN Domain
12.4.4.4
MCAN Functional Description
12.4.4.4.1
Module Clocking Requirements
12.4.4.4.2
Interrupt and DMA Requests
12.4.4.4.2.1
Interrupt Requests
12.4.4.4.2.2
DMA Requests
12.4.4.4.2.3
3064
12.4.4.4.3
Operating Modes
12.4.4.4.3.1
Software Initialization
12.4.4.4.3.2
Normal Operation
12.4.4.4.3.3
CAN FD Operation
12.4.4.4.3.4
Transmitter Delay Compensation
12.4.4.4.3.4.1
Description
12.4.4.4.3.4.2
Transmitter Delay Compensation Measurement
12.4.4.4.3.5
Restricted Operation Mode
12.4.4.4.3.6
Bus Monitoring Mode
12.4.4.4.3.7
Disabled Automatic Retransmission (DAR) Mode
12.4.4.4.3.7.1
Frame Transmission in DAR Mode
12.4.4.4.3.8
Power Down (Sleep Mode)
12.4.4.4.3.8.1
External Clock Stop Mode
12.4.4.4.3.8.2
Suspend Mode
12.4.4.4.3.8.3
Wakeup request
12.4.4.4.3.9
Test Modes
12.4.4.4.3.9.1
Internal Loopback Mode
12.4.4.4.4
Timestamp Generation
12.4.4.4.4.1
External Timestamp Counter
12.4.4.4.5
Timeout Counter
12.4.4.4.6
ECC Support
12.4.4.4.6.1
ECC Wrapper
12.4.4.4.6.2
ECC Aggregator
12.4.4.4.7
Rx Handling
12.4.4.4.7.1
Acceptance Filtering
12.4.4.4.7.1.1
Range Filter
12.4.4.4.7.1.2
Filter for specific IDs
12.4.4.4.7.1.3
Classic Bit Mask Filter
12.4.4.4.7.1.4
Standard Message ID Filtering
12.4.4.4.7.1.5
Extended Message ID Filtering
12.4.4.4.7.2
Rx FIFOs
12.4.4.4.7.2.1
Rx FIFO Blocking Mode
12.4.4.4.7.2.2
Rx FIFO Overwrite Mode
12.4.4.4.7.3
Dedicated Rx Buffers
12.4.4.4.7.3.1
Rx Buffer Handling
12.4.4.4.7.4
Debug on CAN Support
12.4.4.4.8
Tx Handling
12.4.4.4.8.1
Transmit Pause
12.4.4.4.8.2
Dedicated Tx Buffers
12.4.4.4.8.3
Tx FIFO
12.4.4.4.8.4
Tx Queue
12.4.4.4.8.5
Mixed Dedicated Tx Buffers/Tx FIFO
12.4.4.4.8.6
Mixed Dedicated Tx Buffers/Tx Queue
12.4.4.4.8.7
Transmit Cancellation
12.4.4.4.8.8
Tx Event Handling
12.4.4.4.9
FIFO Acknowledge Handling
12.4.4.4.10
Message RAM
12.4.4.4.10.1
Message RAM Configuration
12.4.4.4.10.2
Rx Buffer and FIFO Element
12.4.4.4.10.3
Tx Buffer Element
12.4.4.4.10.4
Tx Event FIFO Element
12.4.4.4.10.5
Standard Message ID Filter Element
12.4.4.4.10.6
Extended Message ID Filter Element
12.4.4.5
MCAN Registers
12.4.4.5.1
MCAN Subsystem Registers
12.4.4.5.2
MCAN Core Registers
12.4.4.5.3
MCAN ECC Aggregator Registers
12.5
Audio Interfaces
12.5.1
Audio Tracking Logic (ATL)
12.5.1.1
ATL Overview
12.5.1.1.1
ATL Features Overview
12.5.1.1.2
ATL Not Supported Features
12.6
Timer Modules
12.6.1
Global Timebase Counter (GTC)
12.6.1.1
GTC Overview
12.6.1.1.1
GTC Features
12.6.1.1.2
GTC Not Supported Features
12.6.1.2
GTC Integration
12.6.1.3
GTC Functional Description
12.6.1.3.1
GTC Block Diagram
12.6.1.3.2
GTC Counter
12.6.1.3.3
GTC Gray Encoder
12.6.1.3.4
GTC Push Event Generation
12.6.1.3.5
GTC Register Partitioning
12.6.1.4
GTC Registers
12.6.1.4.1
GTC0_GTC_CFG0 Registers
12.6.1.4.2
GTC0_GTC_CFG1 Registers
12.6.1.4.3
GTC0_GTC_CFG2 Registers
12.6.1.4.4
GTC0_GTC_CFG3 Registers
12.6.2
Windowed Watchdog Timer (WWDT)
12.6.2.1
RTI Overview
12.6.2.1.1
RTI Features
12.6.2.1.2
RTI Not Supported Features
12.6.2.2
RTI Integration
12.6.2.2.1
RTI Integration in MCU Domain
12.6.2.2.2
RTI Integration in MAIN Domain
12.6.2.3
RTI Functional Description
12.6.2.3.1
RTI Counter Operation
12.6.2.3.2
RTI Digital Watchdog
12.6.2.3.3
RTI Digital Windowed Watchdog
12.6.2.3.4
RTI Low Power Mode Operation
12.6.2.3.5
RTI Debug Mode Behavior
12.6.2.4
RTI Registers
12.6.3
Timers
12.6.3.1
Timers Overview
12.6.3.1.1
Timers Features
12.6.3.1.2
Timers Not Supported Features
12.6.3.2
Timers Environment
12.6.3.2.1
Timer External System Interface
12.6.3.3
Timers Integration
12.6.3.3.1
Timers Integration in MCU Domain
12.6.3.3.2
Timers Integration in MAIN Domain
12.6.3.4
Timers Functional Description
12.6.3.4.1
Timer Block Diagram
12.6.3.4.2
Timer Power Management
12.6.3.4.2.1
Wake-Up Capability
12.6.3.4.3
Timer Software Reset
12.6.3.4.4
Timer Interrupts
12.6.3.4.5
Timer Mode Functionality
12.6.3.4.5.1
1-ms Tick Generation
12.6.3.4.6
Timer Capture Mode Functionality
12.6.3.4.7
Timer Compare Mode Functionality
12.6.3.4.8
Timer Prescaler Functionality
12.6.3.4.9
Timer Pulse-Width Modulation
12.6.3.4.10
Timer Counting Rate
12.6.3.4.11
Timer Under Emulation
12.6.3.4.12
Accessing Timer Registers
12.6.3.4.12.1
Writing to Timer Registers
12.6.3.4.12.1.1
Write Posting Synchronization Mode
12.6.3.4.12.1.2
Write Nonposting Synchronization Mode
12.6.3.4.12.2
Reading From Timer Counter Registers
12.6.3.4.12.2.1
Read Posted
12.6.3.4.12.2.2
Read Non-Posted
12.6.3.4.13
Timer Posted Mode Selection
12.6.3.5
Timers Low-Level Programming Models
12.6.3.5.1
Timer Global Initialization
12.6.3.5.1.1
Global Initialization of Surrounding Modules
12.6.3.5.1.2
Timer Module Global Initialization
12.6.3.5.1.2.1
Main Sequence – Timer Module Global Initialization
12.6.3.5.2
Timer Operational Mode Configuration
12.6.3.5.2.1
Timer Mode
12.6.3.5.2.1.1
Main Sequence – Timer Mode Configuration
12.6.3.5.2.2
Timer Compare Mode
12.6.3.5.2.2.1
Main Sequence – Timer Compare Mode Configuration
12.6.3.5.2.3
Timer Capture Mode
12.6.3.5.2.3.1
Main Sequence – Timer Capture Mode Configuration
12.6.3.5.2.3.2
Subsequence – Initialize Capture Mode
12.6.3.5.2.3.3
Subsequence – Detect Event
12.6.3.5.2.4
Timer PWM Mode
12.6.3.5.2.4.1
Main Sequence – Timer PWM Mode Configuration
12.6.3.6
Timers Registers
12.7
Internal Diagnostics Modules
12.7.1
Dual Clock Comparator (DCC)
12.7.1.1
DCC Overview
12.7.1.1.1
DCC Features
12.7.1.1.2
DCC Not Supported Features
12.7.1.2
DCC Integration
12.7.1.2.1
DCC Integration in MCU Domain
12.7.1.2.2
DCC Integration in MAIN Domain
12.7.1.3
DCC Functional Description
12.7.1.3.1
DCC Counter Operation
12.7.1.3.2
DCC Low Power Mode Operation
12.7.1.3.3
DCC Suspend Mode Behavior
12.7.1.3.4
DCC Single-Shot Mode
12.7.1.3.5
DCC Continuous mode
12.7.1.3.5.1
DCC Continue on Error
12.7.1.3.5.2
DCC Error Count
12.7.1.3.6
DCC Control and count hand-off across clock domains
12.7.1.3.7
DCC Error Trajectory record
12.7.1.3.7.1
DCC FIFO capturing for Errors
12.7.1.3.7.2
DCC FIFO in continuous capture mode
12.7.1.3.7.3
DCC FIFO Details
12.7.1.3.7.4
DCC FIFO Debug mode behavior
12.7.1.3.8
DCC Count read registers
12.7.1.4
DCC Registers
12.7.2
Error Signaling Module (ESM)
12.7.2.1
ESM Overview
12.7.2.1.1
ESM Features
12.7.2.2
ESM Environment
12.7.2.3
ESM Integration
12.7.2.3.1
ESM Integration in WKUP Domain
12.7.2.3.2
ESM Integration in MCU Domain
12.7.2.3.3
ESM Integration in MAIN Domain
12.7.2.4
ESM Functional Description
12.7.2.4.1
ESM Interrupt Requests
12.7.2.4.1.1
ESM Configuration Error Interrupt
12.7.2.4.1.2
ESM Low Priority Error Interrupt
12.7.2.4.1.2.1
ESM Low Priority Error Level Event
12.7.2.4.1.2.2
ESM Low Priority Error Pulse Event
12.7.2.4.1.3
ESM High Priority Error Interrupt
12.7.2.4.1.3.1
ESM High Priority Error Level Event
12.7.2.4.1.3.2
ESM High Priority Error Pulse Event
12.7.2.4.2
ESM Error Event Inputs
12.7.2.4.3
ESM Error Pin Output
12.7.2.4.4
ESM Minimum Time Interval
12.7.2.4.5
ESM Protection for Registers
12.7.2.4.6
ESM Clock Stop
12.7.2.5
ESM Registers
12.7.3
Memory Cyclic Redundancy Check (MCRC) Controller
12.7.3.1
MCRC Overview
12.7.3.1.1
MCRC Features
12.7.3.1.2
MCRC Not Supported Features
12.7.3.2
MCRC Integration
12.7.3.3
MCRC Functional Description
12.7.3.3.1
MCRC Block Diagram
12.7.3.3.2
MCRC General Operation
12.7.3.3.3
MCRC Modes of Operation
12.7.3.3.3.1
AUTO Mode
12.7.3.3.3.2
Semi-CPU Mode
12.7.3.3.3.3
Full-CPU Mode
12.7.3.3.4
PSA Signature Register
12.7.3.3.5
PSA Sector Signature Register
12.7.3.3.6
CRC Value Register
12.7.3.3.7
Raw Data Register
12.7.3.3.8
Example DMA Controller Setup
12.7.3.3.8.1
AUTO Mode Using Hardware Timer Trigger
12.7.3.3.8.2
AUTO Mode Using Software Trigger
12.7.3.3.8.3
Semi-CPU Mode Using Hardware Timer Trigger
12.7.3.3.9
Pattern Count Register
12.7.3.3.10
Sector Count Register/Current Sector Register
12.7.3.3.11
Interrupts
12.7.3.3.11.1
Compression Complete Interrupt
12.7.3.3.11.2
CRC Fail Interrupt
12.7.3.3.11.3
Overrun Interrupt
12.7.3.3.11.4
Underrun Interrupt
12.7.3.3.11.5
Timeout Interrupt
12.7.3.3.11.6
Interrupt Offset Register
12.7.3.3.11.7
Error Handling
12.7.3.3.12
Power Down Mode
12.7.3.3.13
Emulation
12.7.3.4
MCRC Programming Examples
12.7.3.4.1
Example: Auto Mode Using Time Based Event Triggering
12.7.3.4.1.1
DMA Setup
12.7.3.4.1.2
Timer Setup
12.7.3.4.1.3
CRC Setup
12.7.3.4.2
Example: Auto Mode Without Using Time Based Triggering
12.7.3.4.2.1
DMA Setup
12.7.3.4.2.2
CRC Setup
12.7.3.4.3
Example: Semi-CPU Mode
12.7.3.4.3.1
DMA Setup
12.7.3.4.3.2
Timer Setup
12.7.3.4.3.3
CRC Setup
12.7.3.4.4
Example: Full-CPU Mode
12.7.3.4.4.1
CRC Setup
12.7.3.5
MCRC Registers
12.7.4
ECC Aggregator
12.7.4.1
ECC Aggregator Overview
12.7.4.1.1
ECC Aggregator Features
12.7.4.2
ECC Aggregator Integration
12.7.4.3
ECC Aggregator Functional Description
12.7.4.3.1
ECC Aggregator Block Diagram
12.7.4.3.2
ECC Aggregator Register Groups
12.7.4.3.3
Read Access to the ECC Control and Status Registers
12.7.4.3.4
Serial Write Operation
12.7.4.3.5
Interrupts
12.7.4.3.6
Inject Only Mode
12.7.4.4
ECC Aggregator Registers
13
On-Chip Debug
14
Revision History
Technical Reference Manual
J7200 DRA821/AM66A Processor
Texas Instruments Families of Products