JAJSFW1E June   2017  – March 2019 66AK2G12

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  DSS
      2. 4.3.2  DDR EMIF
      3. 4.3.3  GPMC
      4. 4.3.4  Timers
      5. 4.3.5  I2C
      6. 4.3.6  UART
      7. 4.3.7  SPI
      8. 4.3.8  QSPI
      9. 4.3.9  McASP
      10. 4.3.10 USB
      11. 4.3.11 PCIESS
      12. 4.3.12 DCAN
      13. 4.3.13 EMAC
      14. 4.3.14 MLB
      15. 4.3.15 McBSP
      16. 4.3.16 MMC/SD
      17. 4.3.17 GPIO
      18. 4.3.18 ePWM
      19. 4.3.19 PRU-ICSS
      20. 4.3.20 Emulation and Debug Subsystem
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Boot Mode Configuration
        2. 4.3.21.2 Reset
        3. 4.3.21.3 Oscillator Reference Clocks and Clock Generator
        4. 4.3.21.4 Miscellaneous
        5. 4.3.21.5 Interrupt Controllers (INTC)
        6. 4.3.21.6 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On-Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-2  DDR3L SSTL DC Electrical Characteristics
      2. Table 5-3  I2C OPEN DRAIN DC Electrical Characteristics
      3. Table 5-4  Oscillators DC Electrical Characteristics
      4. Table 5-5  LVDS Input Buffer DC Electrical Characteristics
      5. Table 5-6  LVDS Output Buffer DC Electrical Characteristics
      6. Table 5-7  MLB LVDS Buffers DC Electrical Characteristics
      7. Table 5-8  PORn DC Electrical Characteristics
      8. Table 5-9  1.8-Volt I/O LVCMOS DC Electrical Characteristics
      9. Table 5-10 3.3-Volt I/O LVCMOS DC Electrical Characteristics
      10. 5.7.1      USB0_PHY and USB1_PHY DC Electrical Characteristics
      11. 5.7.2      PCIe SERDES DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics for ABY Package
      1. Table 5-11 Thermal Resistance Characteristics for ABY Package
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing
        1. 5.9.1.1 Power-Up Sequence
        2. 5.9.1.2 Power-Down Sequence
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Electrical Data/Timing
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1  Input Clocks / Oscillators
          1. 5.9.3.1.1 System Oscillator (SYSOSC) with External Crystal Circuit
          2. 5.9.3.1.2 System Oscillator (SYSOSC) with External LVCMOS Clock Source
          3. 5.9.3.1.3 System Oscillator (SYSOSC) Not Used
          4. 5.9.3.1.4 Optional LVDS Clock Inputs
        2. 5.9.3.2  Optional LVDS Clock Inputs Not Used
        3. 5.9.3.3  Optional Audio Oscillator (AUDOSC) with External Crystal Circuit
        4. 5.9.3.4  Optional Audio Oscillator (AUDOSC) with External LVCMOS Clock Source
        5. 5.9.3.5  Optional Audio Oscillator (AUDOSC) Not Used
        6. 5.9.3.6  Optional USB PHY Reference Clock
        7. 5.9.3.7  PCIe Reference Clock
        8. 5.9.3.8  Output Clocks
        9. 5.9.3.9  PLLs
          1. 5.9.3.9.1 DDR_PLL Settings
        10. 5.9.3.10 Recommended Clock and Control Signal Transition Behavior
      4. 5.9.4 Peripherals
        1. 5.9.4.1  DCAN
        2. 5.9.4.2  DSS
        3. 5.9.4.3  DDR EMIF
        4. 5.9.4.4  EMAC
          1. 5.9.4.4.1 EMAC MDIO Interface Timings
          2. 5.9.4.4.2 EMAC MII Timings
            1. Table 5-28 Timing Requirements for MII_RXCLK—MII Operation
            2. Table 5-29 Timing Requirements for MII_TXCLK—MII Operation
            3. Table 5-30 Timing Requirements for EMAC MII Receive 10 Mbps and 100 Mbps
            4. Table 5-31 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10 Mbps and 100 Mbps
          3. 5.9.4.4.3 EMAC RMII Timings
            1. Table 5-32 Timing Requirements for EMAC RMII_REFCLK—RMII Operation
            2. Table 5-33 Timing Requirements for EMAC RMII Receive
            3. Table 5-34 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII_REFCLK —RMII Operation
            4. Table 5-35 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 Mbps and 100 Mbps
          4. 5.9.4.4.4 EMAC RGMII Timings
            1. Table 5-36 Timing Requirements for RGMII_RXC—RGMII Operation
            2. Table 5-37 Timing Requirements for EMAC RGMII Input Receive for 10 Mbps, 100 Mbps, and 1000 Mbps
            3. Table 5-38 Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII operation for 10 Mbps, 100 Mbps, and 1000 Mbps
            4. Table 5-39 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII Mode
            5. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode
        5. 5.9.4.5  GPMC
          1. 5.9.4.5.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-41 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-42 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-43 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.4.5.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            2. Table 5-45 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            3. Table 5-46 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        6. 5.9.4.6  I2C
          1. Table 5-47 Timing Requirements for I2C Input Timings
          2. Table 5-48 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        7. 5.9.4.7  McASP
          1. Table 5-49 Timing Requirements for McASP
        8. 5.9.4.8  McBSP
          1. Table 5-51 McBSP Timing Requirements
          2. Table 5-52 McBSP Switching Characteristics
          3. Table 5-53 McBSP Timing Requirements for FSR When GSYNC = 1
        9. 5.9.4.9  MLB
        10. 5.9.4.10 MMC/SD
          1. Table 5-60 MMC Timing Conditions
          2. Table 5-61 Timing Requirements for MMC0_CMD and MMC0_DATn
          3. Table 5-62 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in SDR mode
          4. Table 5-63 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode
          5. Table 5-64 Switching Characteristics for MMCi_CLK
          6. Table 5-65 Switching Characteristics for MMC0_CMD and MMC0_DATn—HSPE=0
          7. Table 5-66 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in SDR mode
          8. Table 5-67 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in DDR mode
        11. 5.9.4.11 PCIESS
        12. 5.9.4.12 PRU-ICSS
          1. 5.9.4.12.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.9.4.12.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-68 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-69 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.9.4.12.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-70 PRU-ICSS PRU Timing Requirements – Parallel Capture Mode
            3. 5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-71 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-72 PRU-ICSS PRU Switching Requirements – Shift Out Mode
          2. 5.9.4.12.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.9.4.12.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-73 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              2. Table 5-74 PRU-ICSS ECAT Timing Requirements – LATCHx_IN
              3. Table 5-75 PRU-ICSS ECAT Switching Requirements – Digital IOs
          3. 5.9.4.12.3 PRU-ICSS MII_RT and Switch
            1. 5.9.4.12.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-76 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-77 PRU-ICSS MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-78 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.4.12.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-79 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-80 PRU-ICSS MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-81 PRU-ICSS MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-82 PRU-ICSS MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
          4. 5.9.4.12.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-83 PRU-ICSS UART Timing Conditions
            2. Table 5-84 Timing Requirements for PRU-ICSS UART Receive
            3. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes
            1. Table 5-86 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            2. Table 5-87 PRU-ICSS PRU Timing Requirements - EnDAT Mode
            3. Table 5-88 PRU-ICSS PRU Switching Requirements - EnDAT Mode
        13. 5.9.4.13 QSPI
        14. 5.9.4.14 SPI
          1. 5.9.4.14.1 SPI—Slave Mode
            1. Table 5-91 Timing Requirements for SPI Input Timings—Slave Mode
            2. Table 5-92 Switching Characteristics for SPI Output Timings—Slave Mode
          2. 5.9.4.14.2 SPI—Master Mode
            1. Table 5-93 SPI Timing Conditions—Master Mode
            2. Table 5-94 Timing Requirements for SPI Input Timings—Master Mode
            3. Table 5-95 Switching Characteristics for SPI Output Timings—Master Mode
        15. 5.9.4.15 Timers
        16. 5.9.4.16 UART
          1. Table 5-98 Timing Requirements for UART
          2. Table 5-99 Switching Characteristics Over Recommended Operating Conditions for UART
        17. 5.9.4.17 USB
      5. 5.9.5 Emulation and Debug Subsystem
        1. 5.9.5.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.5.1.1 JTAG Electrical Data and Timing
            1. Table 5-100 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Arm A15
    4. 6.4  C66x DSP Subsystem
    5. 6.5  C66x Cache Subsystem
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 MSMC
      2. 6.7.2 DDR EMIF
      3. 6.7.3 GPMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MSGMGR
      2. 6.8.2 SEM
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  DCAN
      2. 6.10.2  DSS
      3. 6.10.3  eCAP
      4. 6.10.4  ePWM
      5. 6.10.5  eQEP
      6. 6.10.6  GPIO
      7. 6.10.7  I2C
      8. 6.10.8  ASRC
      9. 6.10.9  McASP
      10. 6.10.10 McBSP
      11. 6.10.11 MLB
      12. 6.10.12 MMC/SD
      13. 6.10.13 NSS
      14. 6.10.14 PCIESS
      15. 6.10.15 QSPI
      16. 6.10.16 SPI
      17. 6.10.17 Timers
      18. 6.10.18 UART
      19. 6.10.19 USB
  7. 7Applications, Implementation, and Layout
    1. 7.1 DDR3L Board Design and Layout Guidelines
      1. 7.1.1 DDR3L General Board Layout Guidelines
      2. 7.1.2 DDR3L Board Design and Layout Guidelines
        1. 7.1.2.1  Board Designs
        2. 7.1.2.2  DDR3L Device Combinations
        3. 7.1.2.3  DDR3L Interface Schematic
          1. 7.1.2.3.1 32-Bit DDR3L Interface
          2. 7.1.2.3.2 16-Bit DDR3L Interface
        4. 7.1.2.4  Compatible JEDEC DDR3L Devices
        5. 7.1.2.5  PCB Stackup
        6. 7.1.2.6  Placement
        7. 7.1.2.7  DDR3L Keepout Region
        8. 7.1.2.8  Bulk Bypass Capacitors
        9. 7.1.2.9  High-Speed Bypass Capacitors
          1. 7.1.2.9.1 Return Current Bypass Capacitors
        10. 7.1.2.10 Net Classes
        11. 7.1.2.11 DDR3L Signal Termination
        12. 7.1.2.12 VREF_DDR Routing
        13. 7.1.2.13 VTT
        14. 7.1.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.1.2.14.1 Four DDR3L Devices
            1. 7.1.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3L Devices
            2. 7.1.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3L Devices
          2. 7.1.2.14.2 One DDR3L Device
            1. 7.1.2.14.2.1 CK and ADDR_CTRL Topologies, One DDR3L Device
            2. 7.1.2.14.2.2 CK and ADDR/CTRL Routing, One DDR3L Device
        15. 7.1.2.15 Data Topologies and Routing Definition
          1. 7.1.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices
          2. 7.1.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices
        16. 7.1.2.16 Routing Specification
          1. 7.1.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 7.1.2.16.2 DQS and DQ Routing Specification
    2. 7.2 High Speed Differential Signal Routing Guidance
    3. 7.3 Power Distribution Network (PDN) Implementation Guidance
      1. 7.3.1 Decoupling/Filtering of Analog Power Supplies and Reference Inputs
        1. 7.3.1.1 PLL Power Supplies
        2. 7.3.1.2 DDR EMIF PHY DLL Power Supplies
        3. 7.3.1.3 DDR EMIF PHY Voltage Reference Input
        4. 7.3.1.4 Internal LDO Outputs
        5. 7.3.1.5 PCIe PHY Power Supply
        6. 7.3.1.6 USB PHY Power Supplies
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
    5. 7.5 Clock Routing Guidelines
      1. 7.5.1 Oscillator Routing
      2. 7.5.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Receiving Notification of Documentation Updates
      1. 8.4.1 静電気放電に関する注意事項
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABY|625
サーマルパッド・メカニカル・データ
発注情報

4.3.17 GPIO

Table 4-18 GPIO Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ABY BALL [4]
GPIO0_00 General-purpose input/output IOZ AC21
GPIO0_01 General-purpose input/output IOZ AE20
GPIO0_02 General-purpose input/output IOZ AD22
GPIO0_03 General-purpose input/output IOZ AD20
GPIO0_04 General-purpose input/output IOZ AE21
GPIO0_05 General-purpose input/output IOZ AE22
GPIO0_06 General-purpose input/output IOZ AC20
GPIO0_07 General-purpose input/output IOZ AD21
GPIO0_08 General-purpose input/output IOZ AE23
GPIO0_09 General-purpose input/output IOZ AB20
GPIO0_10 General-purpose input/output IOZ AA20
GPIO0_11 General-purpose input/output IOZ AD23
GPIO0_12 General-purpose input/output IOZ AA21
GPIO0_13 General-purpose input/output IOZ AB21
GPIO0_14 General-purpose input/output IOZ AB22
GPIO0_15 General-purpose input/output IOZ AA22
GPIO0_16 General-purpose input/output IOZ AB23
GPIO0_17 General-purpose input/output IOZ AC23
GPIO0_18 General-purpose input/output IOZ AC22
GPIO0_19 General-purpose input/output IOZ Y22
GPIO0_100 General-purpose input/output IOZ N3
GPIO0_101 General-purpose input/output IOZ P3
GPIO0_102 General-purpose input/output IOZ P4
GPIO0_103 General-purpose input/output IOZ R2
GPIO0_104 General-purpose input/output IOZ R4
GPIO0_105 General-purpose input/output IOZ R3
GPIO0_106 General-purpose input/output IOZ T2
GPIO0_107 General-purpose input/output IOZ U1
GPIO0_108 General-purpose input/output IOZ D3
GPIO0_109 General-purpose input/output IOZ A2
GPIO0_110 General-purpose input/output IOZ E4
GPIO0_111 General-purpose input/output IOZ B1
GPIO0_112 General-purpose input/output IOZ A3
GPIO0_113 General-purpose input/output IOZ E5
GPIO0_114 General-purpose input/output IOZ B2
GPIO0_115 General-purpose input/output IOZ D4
GPIO0_116 General-purpose input/output IOZ E6
GPIO0_117 General-purpose input/output IOZ C2
GPIO0_118 General-purpose input/output IOZ C3
GPIO0_119 General-purpose input/output IOZ D5
GPIO0_120 General-purpose input/output IOZ B3
GPIO0_121 General-purpose input/output IOZ B4
GPIO0_122 General-purpose input/output IOZ A4
GPIO0_123 General-purpose input/output IOZ E7
GPIO0_124 General-purpose input/output IOZ D6
GPIO0_125 General-purpose input/output IOZ C4
GPIO0_126 General-purpose input/output IOZ C5
GPIO0_127 General-purpose input/output IOZ A5
GPIO0_128 General-purpose input/output IOZ B5
GPIO0_129 General-purpose input/output IOZ B6
GPIO0_130 General-purpose input/output IOZ D7
GPIO0_131 General-purpose input/output IOZ A6
GPIO0_132 General-purpose input/output IOZ C6
GPIO0_133 General-purpose input/output IOZ E8
GPIO0_134 General-purpose input/output IOZ A7
GPIO0_135 General-purpose input/output IOZ D8
GPIO0_136 General-purpose input/output IOZ F9
GPIO0_137 General-purpose input/output IOZ B7
GPIO0_138 General-purpose input/output IOZ C7
GPIO0_139 General-purpose input/output IOZ E9
GPIO0_140 General-purpose input/output IOZ A8
GPIO0_141 General-purpose input/output IOZ B8
GPIO0_142 General-purpose input/output IOZ D9
GPIO0_143 General-purpose input/output IOZ C8
GPIO0_20 General-purpose input/output IOZ AC24
GPIO0_21 General-purpose input/output IOZ AB24
GPIO0_22 General-purpose input/output IOZ Y24
GPIO0_23 General-purpose input/output IOZ AA24
GPIO0_24 General-purpose input/output IOZ W25
GPIO0_25 General-purpose input/output IOZ AA25
GPIO0_26 General-purpose input/output IOZ AB25
GPIO0_27 General-purpose input/output IOZ W24
GPIO0_28 General-purpose input/output IOZ W23
GPIO0_29 General-purpose input/output IOZ Y25
GPIO0_30 General-purpose input/output IOZ N23
GPIO0_31 General-purpose input/output IOZ P25
GPIO0_32 General-purpose input/output IOZ P24
GPIO0_33 General-purpose input/output IOZ N24
GPIO0_34 General-purpose input/output IOZ T25
GPIO0_35 General-purpose input/output IOZ N22
GPIO0_36 General-purpose input/output IOZ R24
GPIO0_37 General-purpose input/output IOZ P23
GPIO0_38 General-purpose input/output IOZ R22
GPIO0_39 General-purpose input/output IOZ U25
GPIO0_40 General-purpose input/output IOZ P21
GPIO0_41 General-purpose input/output IOZ T24
GPIO0_42 General-purpose input/output IOZ V25
GPIO0_43 General-purpose input/output IOZ U24
GPIO0_44 General-purpose input/output IOZ R21
GPIO0_45 General-purpose input/output IOZ T22
GPIO0_46 General-purpose input/output IOZ U22
GPIO0_47 General-purpose input/output IOZ T21
GPIO0_48 General-purpose input/output IOZ V24
GPIO0_49 General-purpose input/output IOZ U23
GPIO0_50 General-purpose input/output IOZ V23
GPIO0_51 General-purpose input/output IOZ W22
GPIO0_52 General-purpose input/output IOZ U21
GPIO0_53 General-purpose input/output IOZ V22
GPIO0_54 General-purpose input/output IOZ R25
GPIO0_55 General-purpose input/output IOZ P22
GPIO0_56 General-purpose input/output IOZ N25
GPIO0_57 General-purpose input/output IOZ M25
GPIO0_58 General-purpose input/output IOZ L25
GPIO0_59 General-purpose input/output IOZ G5
GPIO0_60 General-purpose input/output IOZ F4
GPIO0_61 General-purpose input/output IOZ G4
GPIO0_62 General-purpose input/output IOZ E3
GPIO0_63 General-purpose input/output IOZ H4
GPIO0_64 General-purpose input/output IOZ J5
GPIO0_65 General-purpose input/output IOZ F5
GPIO0_66 General-purpose input/output IOZ H3
GPIO0_67 General-purpose input/output IOZ J4
GPIO0_68 General-purpose input/output IOZ J2
GPIO0_69 General-purpose input/output IOZ J3
GPIO0_70 General-purpose input/output IOZ K3
GPIO0_71 General-purpose input/output IOZ K2
GPIO0_72 General-purpose input/output IOZ A22
GPIO0_73 General-purpose input/output IOZ A23
GPIO0_74 General-purpose input/output IOZ B22
GPIO0_75 General-purpose input/output IOZ C22
GPIO0_76 General-purpose input/output IOZ D23
GPIO0_77 General-purpose input/output IOZ F22
GPIO0_78 General-purpose input/output IOZ B23
GPIO0_79 General-purpose input/output IOZ C23
GPIO0_80 General-purpose input/output IOZ B24
GPIO0_81 General-purpose input/output IOZ A24
GPIO0_82 General-purpose input/output IOZ F23
GPIO0_83 General-purpose input/output IOZ B25
GPIO0_84 General-purpose input/output IOZ G22
GPIO0_85 General-purpose input/output IOZ C25
GPIO0_86 General-purpose input/output IOZ C24
GPIO0_87 General-purpose input/output IOZ E25
GPIO0_88 General-purpose input/output IOZ E24
GPIO0_89 General-purpose input/output IOZ F25
GPIO0_90 General-purpose input/output IOZ F24
GPIO0_91 General-purpose input/output IOZ D25
GPIO0_92 General-purpose input/output IOZ G25
GPIO0_93 General-purpose input/output IOZ G24
GPIO0_94 General-purpose input/output IOZ G23
GPIO0_95 General-purpose input/output IOZ H25
GPIO0_96 General-purpose input/output IOZ H24
GPIO0_97 General-purpose input/output IOZ V3
GPIO0_98 General-purpose input/output IOZ U3
GPIO0_99 General-purpose input/output IOZ M4
GPIO1_00 General-purpose input/output IOZ C9
GPIO1_01 General-purpose input/output IOZ B9
GPIO1_02 General-purpose input/output IOZ A9
GPIO1_03 General-purpose input/output IOZ B10
GPIO1_04 General-purpose input/output IOZ A10
GPIO1_05 General-purpose input/output IOZ C10
GPIO1_06 General-purpose input/output IOZ E10
GPIO1_07 General-purpose input/output IOZ D10
GPIO1_08 General-purpose input/output IOZ F10
GPIO1_09 General-purpose input/output IOZ C11
GPIO1_10 General-purpose input/output IOZ D11
GPIO1_11 General-purpose input/output IOZ E11
GPIO1_12 General-purpose input/output IOZ F12
GPIO1_13 General-purpose input/output IOZ E12
GPIO1_14 General-purpose input/output IOZ C12
GPIO1_15 General-purpose input/output IOZ B11
GPIO1_16 General-purpose input/output IOZ B12
GPIO1_17 General-purpose input/output IOZ A12
GPIO1_18 General-purpose input/output IOZ A11
GPIO1_19 General-purpose input/output IOZ A13
GPIO1_20 General-purpose input/output IOZ B13
GPIO1_21 General-purpose input/output IOZ F13
GPIO1_22 General-purpose input/output IOZ C13
GPIO1_23 General-purpose input/output IOZ E13
GPIO1_24 General-purpose input/output IOZ D12
GPIO1_25 General-purpose input/output IOZ D13
GPIO1_26 General-purpose input/output IOZ A14
GPIO1_27 General-purpose input/output IOZ B14
GPIO1_28 General-purpose input/output IOZ C14
GPIO1_29 General-purpose input/output IOZ E14
GPIO1_30 General-purpose input/output IOZ D14
GPIO1_31 General-purpose input/output IOZ A15
GPIO1_32 General-purpose input/output IOZ F14
GPIO1_33 General-purpose input/output IOZ B15
GPIO1_34 General-purpose input/output IOZ C15
GPIO1_35 General-purpose input/output IOZ D15
GPIO1_36 General-purpose input/output IOZ A16
GPIO1_37 General-purpose input/output IOZ E15
GPIO1_38 General-purpose input/output IOZ B16
GPIO1_39 General-purpose input/output IOZ C16
GPIO1_40 General-purpose input/output IOZ D17
GPIO1_41 General-purpose input/output IOZ C18
GPIO1_42 General-purpose input/output IOZ D16
GPIO1_43 General-purpose input/output IOZ F16
GPIO1_44 General-purpose input/output IOZ E17
GPIO1_45 General-purpose input/output IOZ E16
GPIO1_46 General-purpose input/output IOZ E18
GPIO1_47 General-purpose input/output IOZ D18
GPIO1_48 General-purpose input/output IOZ T3
GPIO1_49 General-purpose input/output IOZ T5
GPIO1_50 General-purpose input/output IOZ U2
GPIO1_51 General-purpose input/output IOZ U4
GPIO1_52 General-purpose input/output IOZ E21
GPIO1_53 General-purpose input/output IOZ D21
GPIO1_54 General-purpose input/output IOZ D22
GPIO1_55 General-purpose input/output IOZ C21
GPIO1_56 General-purpose input/output IOZ P5
GPIO1_57 General-purpose input/output IOZ R5
GPIO1_58 General-purpose input/output IOZ K25
GPIO1_59 General-purpose input/output IOZ K24
GPIO1_60 General-purpose input/output IOZ J23
GPIO1_61 General-purpose input/output IOZ J22
GPIO1_62 General-purpose input/output IOZ J21
GPIO1_63 General-purpose input/output IOZ J24
GPIO1_64 General-purpose input/output IOZ J25
GPIO1_65 General-purpose input/output IOZ H23
GPIO1_66 General-purpose input/output IOZ H22
GPIO1_67 General-purpose input/output IOZ H21

For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the Device TRM.