JAJSFW1E June   2017  – March 2019 66AK2G12

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  DSS
      2. 4.3.2  DDR EMIF
      3. 4.3.3  GPMC
      4. 4.3.4  Timers
      5. 4.3.5  I2C
      6. 4.3.6  UART
      7. 4.3.7  SPI
      8. 4.3.8  QSPI
      9. 4.3.9  McASP
      10. 4.3.10 USB
      11. 4.3.11 PCIESS
      12. 4.3.12 DCAN
      13. 4.3.13 EMAC
      14. 4.3.14 MLB
      15. 4.3.15 McBSP
      16. 4.3.16 MMC/SD
      17. 4.3.17 GPIO
      18. 4.3.18 ePWM
      19. 4.3.19 PRU-ICSS
      20. 4.3.20 Emulation and Debug Subsystem
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Boot Mode Configuration
        2. 4.3.21.2 Reset
        3. 4.3.21.3 Oscillator Reference Clocks and Clock Generator
        4. 4.3.21.4 Miscellaneous
        5. 4.3.21.5 Interrupt Controllers (INTC)
        6. 4.3.21.6 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On-Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-2  DDR3L SSTL DC Electrical Characteristics
      2. Table 5-3  I2C OPEN DRAIN DC Electrical Characteristics
      3. Table 5-4  Oscillators DC Electrical Characteristics
      4. Table 5-5  LVDS Input Buffer DC Electrical Characteristics
      5. Table 5-6  LVDS Output Buffer DC Electrical Characteristics
      6. Table 5-7  MLB LVDS Buffers DC Electrical Characteristics
      7. Table 5-8  PORn DC Electrical Characteristics
      8. Table 5-9  1.8-Volt I/O LVCMOS DC Electrical Characteristics
      9. Table 5-10 3.3-Volt I/O LVCMOS DC Electrical Characteristics
      10. 5.7.1      USB0_PHY and USB1_PHY DC Electrical Characteristics
      11. 5.7.2      PCIe SERDES DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics for ABY Package
      1. Table 5-11 Thermal Resistance Characteristics for ABY Package
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing
        1. 5.9.1.1 Power-Up Sequence
        2. 5.9.1.2 Power-Down Sequence
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Electrical Data/Timing
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1  Input Clocks / Oscillators
          1. 5.9.3.1.1 System Oscillator (SYSOSC) with External Crystal Circuit
          2. 5.9.3.1.2 System Oscillator (SYSOSC) with External LVCMOS Clock Source
          3. 5.9.3.1.3 System Oscillator (SYSOSC) Not Used
          4. 5.9.3.1.4 Optional LVDS Clock Inputs
        2. 5.9.3.2  Optional LVDS Clock Inputs Not Used
        3. 5.9.3.3  Optional Audio Oscillator (AUDOSC) with External Crystal Circuit
        4. 5.9.3.4  Optional Audio Oscillator (AUDOSC) with External LVCMOS Clock Source
        5. 5.9.3.5  Optional Audio Oscillator (AUDOSC) Not Used
        6. 5.9.3.6  Optional USB PHY Reference Clock
        7. 5.9.3.7  PCIe Reference Clock
        8. 5.9.3.8  Output Clocks
        9. 5.9.3.9  PLLs
          1. 5.9.3.9.1 DDR_PLL Settings
        10. 5.9.3.10 Recommended Clock and Control Signal Transition Behavior
      4. 5.9.4 Peripherals
        1. 5.9.4.1  DCAN
        2. 5.9.4.2  DSS
        3. 5.9.4.3  DDR EMIF
        4. 5.9.4.4  EMAC
          1. 5.9.4.4.1 EMAC MDIO Interface Timings
          2. 5.9.4.4.2 EMAC MII Timings
            1. Table 5-28 Timing Requirements for MII_RXCLK—MII Operation
            2. Table 5-29 Timing Requirements for MII_TXCLK—MII Operation
            3. Table 5-30 Timing Requirements for EMAC MII Receive 10 Mbps and 100 Mbps
            4. Table 5-31 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10 Mbps and 100 Mbps
          3. 5.9.4.4.3 EMAC RMII Timings
            1. Table 5-32 Timing Requirements for EMAC RMII_REFCLK—RMII Operation
            2. Table 5-33 Timing Requirements for EMAC RMII Receive
            3. Table 5-34 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII_REFCLK —RMII Operation
            4. Table 5-35 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 Mbps and 100 Mbps
          4. 5.9.4.4.4 EMAC RGMII Timings
            1. Table 5-36 Timing Requirements for RGMII_RXC—RGMII Operation
            2. Table 5-37 Timing Requirements for EMAC RGMII Input Receive for 10 Mbps, 100 Mbps, and 1000 Mbps
            3. Table 5-38 Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII operation for 10 Mbps, 100 Mbps, and 1000 Mbps
            4. Table 5-39 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII Mode
            5. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode
        5. 5.9.4.5  GPMC
          1. 5.9.4.5.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-41 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-42 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-43 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.4.5.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            2. Table 5-45 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            3. Table 5-46 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        6. 5.9.4.6  I2C
          1. Table 5-47 Timing Requirements for I2C Input Timings
          2. Table 5-48 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        7. 5.9.4.7  McASP
          1. Table 5-49 Timing Requirements for McASP
        8. 5.9.4.8  McBSP
          1. Table 5-51 McBSP Timing Requirements
          2. Table 5-52 McBSP Switching Characteristics
          3. Table 5-53 McBSP Timing Requirements for FSR When GSYNC = 1
        9. 5.9.4.9  MLB
        10. 5.9.4.10 MMC/SD
          1. Table 5-60 MMC Timing Conditions
          2. Table 5-61 Timing Requirements for MMC0_CMD and MMC0_DATn
          3. Table 5-62 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in SDR mode
          4. Table 5-63 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode
          5. Table 5-64 Switching Characteristics for MMCi_CLK
          6. Table 5-65 Switching Characteristics for MMC0_CMD and MMC0_DATn—HSPE=0
          7. Table 5-66 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in SDR mode
          8. Table 5-67 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in DDR mode
        11. 5.9.4.11 PCIESS
        12. 5.9.4.12 PRU-ICSS
          1. 5.9.4.12.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.9.4.12.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-68 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-69 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.9.4.12.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-70 PRU-ICSS PRU Timing Requirements – Parallel Capture Mode
            3. 5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-71 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-72 PRU-ICSS PRU Switching Requirements – Shift Out Mode
          2. 5.9.4.12.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.9.4.12.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-73 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              2. Table 5-74 PRU-ICSS ECAT Timing Requirements – LATCHx_IN
              3. Table 5-75 PRU-ICSS ECAT Switching Requirements – Digital IOs
          3. 5.9.4.12.3 PRU-ICSS MII_RT and Switch
            1. 5.9.4.12.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-76 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-77 PRU-ICSS MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-78 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.4.12.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-79 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-80 PRU-ICSS MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-81 PRU-ICSS MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-82 PRU-ICSS MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
          4. 5.9.4.12.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-83 PRU-ICSS UART Timing Conditions
            2. Table 5-84 Timing Requirements for PRU-ICSS UART Receive
            3. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes
            1. Table 5-86 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            2. Table 5-87 PRU-ICSS PRU Timing Requirements - EnDAT Mode
            3. Table 5-88 PRU-ICSS PRU Switching Requirements - EnDAT Mode
        13. 5.9.4.13 QSPI
        14. 5.9.4.14 SPI
          1. 5.9.4.14.1 SPI—Slave Mode
            1. Table 5-91 Timing Requirements for SPI Input Timings—Slave Mode
            2. Table 5-92 Switching Characteristics for SPI Output Timings—Slave Mode
          2. 5.9.4.14.2 SPI—Master Mode
            1. Table 5-93 SPI Timing Conditions—Master Mode
            2. Table 5-94 Timing Requirements for SPI Input Timings—Master Mode
            3. Table 5-95 Switching Characteristics for SPI Output Timings—Master Mode
        15. 5.9.4.15 Timers
        16. 5.9.4.16 UART
          1. Table 5-98 Timing Requirements for UART
          2. Table 5-99 Switching Characteristics Over Recommended Operating Conditions for UART
        17. 5.9.4.17 USB
      5. 5.9.5 Emulation and Debug Subsystem
        1. 5.9.5.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.5.1.1 JTAG Electrical Data and Timing
            1. Table 5-100 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Arm A15
    4. 6.4  C66x DSP Subsystem
    5. 6.5  C66x Cache Subsystem
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 MSMC
      2. 6.7.2 DDR EMIF
      3. 6.7.3 GPMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MSGMGR
      2. 6.8.2 SEM
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  DCAN
      2. 6.10.2  DSS
      3. 6.10.3  eCAP
      4. 6.10.4  ePWM
      5. 6.10.5  eQEP
      6. 6.10.6  GPIO
      7. 6.10.7  I2C
      8. 6.10.8  ASRC
      9. 6.10.9  McASP
      10. 6.10.10 McBSP
      11. 6.10.11 MLB
      12. 6.10.12 MMC/SD
      13. 6.10.13 NSS
      14. 6.10.14 PCIESS
      15. 6.10.15 QSPI
      16. 6.10.16 SPI
      17. 6.10.17 Timers
      18. 6.10.18 UART
      19. 6.10.19 USB
  7. 7Applications, Implementation, and Layout
    1. 7.1 DDR3L Board Design and Layout Guidelines
      1. 7.1.1 DDR3L General Board Layout Guidelines
      2. 7.1.2 DDR3L Board Design and Layout Guidelines
        1. 7.1.2.1  Board Designs
        2. 7.1.2.2  DDR3L Device Combinations
        3. 7.1.2.3  DDR3L Interface Schematic
          1. 7.1.2.3.1 32-Bit DDR3L Interface
          2. 7.1.2.3.2 16-Bit DDR3L Interface
        4. 7.1.2.4  Compatible JEDEC DDR3L Devices
        5. 7.1.2.5  PCB Stackup
        6. 7.1.2.6  Placement
        7. 7.1.2.7  DDR3L Keepout Region
        8. 7.1.2.8  Bulk Bypass Capacitors
        9. 7.1.2.9  High-Speed Bypass Capacitors
          1. 7.1.2.9.1 Return Current Bypass Capacitors
        10. 7.1.2.10 Net Classes
        11. 7.1.2.11 DDR3L Signal Termination
        12. 7.1.2.12 VREF_DDR Routing
        13. 7.1.2.13 VTT
        14. 7.1.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.1.2.14.1 Four DDR3L Devices
            1. 7.1.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3L Devices
            2. 7.1.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3L Devices
          2. 7.1.2.14.2 One DDR3L Device
            1. 7.1.2.14.2.1 CK and ADDR_CTRL Topologies, One DDR3L Device
            2. 7.1.2.14.2.2 CK and ADDR/CTRL Routing, One DDR3L Device
        15. 7.1.2.15 Data Topologies and Routing Definition
          1. 7.1.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices
          2. 7.1.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices
        16. 7.1.2.16 Routing Specification
          1. 7.1.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 7.1.2.16.2 DQS and DQ Routing Specification
    2. 7.2 High Speed Differential Signal Routing Guidance
    3. 7.3 Power Distribution Network (PDN) Implementation Guidance
      1. 7.3.1 Decoupling/Filtering of Analog Power Supplies and Reference Inputs
        1. 7.3.1.1 PLL Power Supplies
        2. 7.3.1.2 DDR EMIF PHY DLL Power Supplies
        3. 7.3.1.3 DDR EMIF PHY Voltage Reference Input
        4. 7.3.1.4 Internal LDO Outputs
        5. 7.3.1.5 PCIe PHY Power Supply
        6. 7.3.1.6 USB PHY Power Supplies
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
    5. 7.5 Clock Routing Guidelines
      1. 7.5.1 Oscillator Routing
      2. 7.5.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Receiving Notification of Documentation Updates
      1. 8.4.1 静電気放電に関する注意事項
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABY|625
サーマルパッド・メカニカル・データ
発注情報

4.4 Pin Multiplexing

Table 4-28 describes the signal multiplexing associated with pins.

NOTE

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions.

Table 4-28, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Refer to the respective peripheral chapter of the Device TRM for information associated with peripheral signal multiplexing.

NOTE

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

NOTE

Any balls without an associated pin multiplexing register have a dedicated function that is defined in the MUXMODE "0" column of this table.

For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM.

Table 4-28 Pin Multiplexing

ADDRESS OFFSET REGISTER NAME BALL NUMBER MUXMODE AND BOOTSTRAP SETTINGS
0 1 2 3 4 5 Bootstrap
R1 SYSCLKSEL
Y15 DDR3_A01
AB4 DDR3_DQM0
L1 OBSCLK_N
Y6 DDR3_D10
AE15 DDR3_CLKOUT_P0
AA3 PORn
AA17 DDR3_A12
AE7 DDR3_D22
A19 USB0_ID
AB16 DDR3_A04
C19 USB0_TXRTUNE_RKELVIN
AE9 DDR3_DQS3_P
W2 RESETFULLn
A21 USB1_VBUS
AE4 DDR3_DQS1_N
V9 DDR3_RZQ1
AD16 DDR3_CLKOUT_N1
AE19 SYSOSC_OUT
L24 MLBP_SIG_P
AC11 DDR3_CB02
K1 OBSCLK_P
L22 EMU01
A20 USB1_DM
AD1 DDR3_DQS0_P
AE3 DDR3_D04
H7 PCIE_REFRES
K22 MLBP_DAT_N
AA8 DDR3_D20
AC14 DDR3_A06
AB8 DDR3_D17
AC17 DDR3_A08
AC6 DDR3_D21
W3 RESETn
AD6 DDR3_DQS2_N
AA9 DDR3_DQM3
AB10 DDR3_D29
AA12 DDR3_A13
Y16 DDR3_A15
AA4 DDR3_D05
AA16 DDR3_A11
AA5 DDR3_DQM1
C17 AUDOSC_IN
AB15 DDR3_A07
D20 USB1_TXRTUNE_RKELVIN
Y5 DDR3_D13
F2 PCIE_CLK_N
L23 MLBP_CLK_N
AD13 DDR3_CEn0
AB9 DDR3_D30
D19 USB0_XO
AC25 SYSCLK_N
AE16 DDR3_CLKOUT_P1
L21 CPTS_REFCLK_N
W12 DDR3_RZQ0
AE24 DDR_CLK_P
AB5 DDR3_D15
AC15 DDR3_A00
AE10 DDR3_D25
AA15 DDR3_A03
M24 MLBP_SIG_N
E1 PCIE_RXP0
AD17 DDR3_BA2
AC3 DDR3_D02
K5 TDO
AC7 DDR3_D18
AD9 DDR3_DQS3_N
Y8 DDR3_D31
L3 TCK
K23 MLBP_DAT_P
Y11 DDR3_CBDQM
AB14 DDR3_A10
Y13 DDR3_WEn
A18 USB0_DP
AD24 DDR_CLK_N
Y17 DDR3_A14
AC8 DDR3_DQM2
AC12 DDR3_CB03
AA6 DDR3_D08
AD7 DDR3_D23
B19 USB0_VBUS
AA11 DDR3_CB00
AC10 DDR3_D27
AE17 DDR3_A05
AE12 DDR3_CBDQS_P
AA14 DDR3_BA0
G2 PCIE_CLK_P
AC4 DDR3_D14
Y9 DDR3_VREFSSTL
H1 PCIE_TXN0
AB18 DDR3_CKE0
AB6 DDR3_D12
E20 USB1_ID
L4 TRSTn
AC19 SYSOSC_IN
AD3 DDR3_D06
B20 USB1_DP
AE6 DDR3_DQS2_P
AB7 DDR3_D16
M22 EMU00
D1 PCIE_RXN0
M23 MLBP_CLK_P
AB3 DDR3_D07
AD2 DDR3_D00
A17 AUDOSC_OUT
B18 USB0_DM
AB13 DDR3_BA1
K4 TMS
AB17 DDR3_A09
Y7 DDR3_D09
AD15 DDR3_CLKOUT_N0
Y18 DDR3_RESETn
AC13 DDR3_CASn
AC2 DDR3_D03
G1 PCIE_TXP0
AD12 DDR3_CBDQS_N
AD10 DDR3_D26
AE13 DDR3_RASn
AE2 DDR3_DQS0_N
AA13 DDR3_ODT0
C20 USB1_XO
L5 TDI
AA10 DDR3_D24
K21 CPTS_REFCLK_P
AA7 DDR3_D19
AC5 DDR3_D11
Y4 DDR3_D01
AC16 DDR3_A02
AB11 DDR3_CB01
AD25 SYSCLK_P
AC9 DDR3_D28
AD4 DDR3_DQS1_P
U5 I2C0_SCL
W5 I2C0_SDA
V6 I2C1_SCL
W4 I2C1_SDA
V5 I2C2_SCL
V4 I2C2_SDA
0x1000 PADCONFIG_0 AC21 GPMC_AD0 GPIO0_00
0x1004 PADCONFIG_1 AE20 GPMC_AD1 GPIO0_01
0x1008 PADCONFIG_2 AD22 GPMC_AD2 GPIO0_02
0x100C PADCONFIG_3 AD20 GPMC_AD3 GPIO0_03
0x1010 PADCONFIG_4 AE21 GPMC_AD4 GPIO0_04
0x1014 PADCONFIG_5 AE22 GPMC_AD5 GPIO0_05
0x1018 PADCONFIG_6 AC20 GPMC_AD6 GPIO0_06
0x101C PADCONFIG_7 AD21 GPMC_AD7 GPIO0_07
0x1020 PADCONFIG_8 AE23 GPMC_AD8 GPIO0_08
0x1024 PADCONFIG_9 AB20 GPMC_AD9 GPIO0_09
0x1028 PADCONFIG_10 AA20 GPMC_AD10 GPIO0_10
0x102C PADCONFIG_11 AD23 GPMC_AD11 GPIO0_11
0x1030 PADCONFIG_12 AA21 GPMC_AD12 GPIO0_12
0x1034 PADCONFIG_13 AB21 GPMC_AD13 GPIO0_13
0x1038 PADCONFIG_14 AB22 GPMC_AD14 GPIO0_14
0x103C PADCONFIG_15 AA22 GPMC_AD15 GPIO0_15
0x1040 PADCONFIG_16 AB23 GPMC_CLK GPIO0_16
0x1044 PADCONFIG_17 AC23 GPMC_ADVn_ALE GPIO0_17
0x1048 PADCONFIG_18 AC22 GPMC_OEn_REn GPIO0_18
0x104C PADCONFIG_19 Y22 GPMC_WEn GPIO0_19
0x1050 PADCONFIG_20 AC24 GPMC_BEn0_CLE GPIO0_20
0x1054 PADCONFIG_21 AB24 GPMC_BEn1 GPIO0_21
0x1058 PADCONFIG_22 Y24 GPMC_WAIT0 GPIO0_22
0x105C PADCONFIG_23 AA24 GPMC_WAIT1 MLB_CLK GPIO0_23
0x1060 PADCONFIG_24 W25 GPMC_WPn GPIO0_24
0x1064 PADCONFIG_25 AA25 GPMC_DIR MLB_SIG GPIO0_25
0x1068 PADCONFIG_26 AB25 GPMC_CSn0 GPIO0_26
0x106C PADCONFIG_27 W24 GPMC_CSn1 MLB_DAT GPIO0_27
0x1070 PADCONFIG_28 W23 GPMC_CSn2 TIMI1 GPIO0_28
0x1074 PADCONFIG_29 Y25 GPMC_CSn3 TIMO1 GPIO0_29
0x1078 PADCONFIG_30 N23 DSS_DATA23 GPMC_A24 eHRPWM0_A GPIO0_30 EMU02 BOOTMODE00
0x107C PADCONFIG_31 P25 DSS_DATA22 GPMC_A23 eHRPWM0_B GPIO0_31 EMU03 BOOTMODE01
0x1080 PADCONFIG_32 P24 DSS_DATA21 GPMC_A22 eHRPWM_TZn0 GPIO0_32 EMU04 BOOTMODE02
0x1084 PADCONFIG_33 N24 DSS_DATA20 GPMC_A21 eHRPWM0_SYNCI GPIO0_33 EMU05 BOOTMODE03
0x1088 PADCONFIG_34 T25 DSS_DATA19 GPMC_A20 eHRPWM0_SYNCO GPIO0_34 EMU06 DSS_RFBI_TEVSYNC1 BOOTMODE04
0x108C PADCONFIG_35 N22 DSS_DATA18 GPMC_A19 eHRPWM1_A GPIO0_35 EMU07 DSS_RFBI_HSYNC1 BOOTMODE05
0x1090 PADCONFIG_36 R24 DSS_DATA17 GPMC_A18 eHRPWM1_B GPIO0_36 EMU08 DSS_RFBI_CSn1 BOOTMODE06
0x1094 PADCONFIG_37 P23 DSS_DATA16 GPMC_A17 eHRPWM_TZn1 GPIO0_37 EMU09 DSS_RFBI_CSn0 BOOTMODE07
0x1098 PADCONFIG_38 R22 DSS_DATA15 GPMC_A16 eHRPWM2_A GPIO0_38 EMU10 DSS_RFBI_DATA15 BOOTMODE08
0x109C PADCONFIG_39 U25 DSS_DATA14 GPMC_A15 eHRPWM2_B GPIO0_39 EMU11 DSS_RFBI_DATA14 BOOTMODE09
0x10A0 PADCONFIG_40 P21 DSS_DATA13 GPMC_A14 eHRPWM_TZn2 GPIO0_40 EMU12 DSS_RFBI_DATA13 BOOTMODE10
0x10A4 PADCONFIG_41 T24 DSS_DATA12 GPMC_A13 eQEP0_A GPIO0_41 EMU13 DSS_RFBI_DATA12 BOOTMODE11
0x10A8 PADCONFIG_42 V25 DSS_DATA11 GPMC_A12 eQEP0_B GPIO0_42 EMU14 DSS_RFBI_DATA11 BOOTMODE12
0x10AC PADCONFIG_43 U24 DSS_DATA10 GPMC_A11 eQEP0_I GPIO0_43 EMU15 DSS_RFBI_DATA10 BOOTMODE13
0x10B0 PADCONFIG_44 R21 DSS_DATA9 GPMC_A10 eQEP0_S GPIO0_44 EMU16 DSS_RFBI_DATA9 BOOTMODE14
0x10B4 PADCONFIG_45 T22 DSS_DATA8 GPMC_A9 eQEP1_A GPIO0_45 EMU17 DSS_RFBI_DATA8 BOOTMODE15
0x10B8 PADCONFIG_46 U22 DSS_DATA7 GPMC_A8 eQEP1_B GPIO0_46 EMU18 DSS_RFBI_DATA7
0x10BC PADCONFIG_47 T21 DSS_DATA6 GPMC_A7 eQEP1_I GPIO0_47 EMU19 DSS_RFBI_DATA6
0x10C0 PADCONFIG_48 V24 DSS_DATA5 GPMC_A6 eQEP1_S GPIO0_48 DSS_RFBI_DATA5
0x10C4 PADCONFIG_49 U23 DSS_DATA4 GPMC_A5 eQEP2_A GPIO0_49 DSS_RFBI_DATA4 NODDR
0x10C8 PADCONFIG_50 V23 DSS_DATA3 GPMC_A4 eQEP2_B GPIO0_50 DSS_RFBI_DATA3 BOOT_RSVD
0x10CC PADCONFIG_51 W22 DSS_DATA2 GPMC_A3 eQEP2_I GPIO0_51 DSS_RFBI_DATA2 MAINPLL_OD_SEL
0x10D0 PADCONFIG_52 U21 DSS_DATA1 GPMC_A2 eQEP2_S GPIO0_52 DSS_RFBI_DATA1
0x10D4 PADCONFIG_53 V22 DSS_DATA0 GPMC_A1 GPIO0_53 DSS_RFBI_DATA0
0x10D8 PADCONFIG_54 R25 DSS_VSYNC GPMC_A25 PR1_eCAP0_eCAP_CAPIN_APWM_O GPIO0_54 DSS_RFBI_TEVSYNC0
0x10DC PADCONFIG_55 P22 DSS_HSYNC GPMC_A26 PR1_eCAP0_eCAP_SYNCIN GPIO0_55 DSS_RFBI_HSYNC0
0x10E0 PADCONFIG_56 N25 DSS_PCLK GPMC_A27 PR1_eCAP0_eCAP_SYNCOUT GPIO0_56 DSS_RFBI_REn
0x10E4 PADCONFIG_57 M25 DSS_DE GPMC_A0 PR1_EDIO_OUTVALID GPIO0_57 DSS_RFBI_WEn
0x10E8 PADCONFIG_58 L25 DSS_FID PR0_EDIO_OUTVALID GPIO0_58 DSS_RFBI_A0
0x10EC PADCONFIG_59 G5 MMC1_DAT7 GPIO0_59
0x10F0 PADCONFIG_60 F4 MMC1_DAT6 GPIO0_60
0x10F4 PADCONFIG_61 G4 MMC1_DAT5 GPIO0_61
0x10F8 PADCONFIG_62 E3 MMC1_DAT4 GPIO0_62
0x10FC PADCONFIG_63 H4 MMC1_DAT3 GPIO0_63
0x1100 PADCONFIG_64 J5 MMC1_DAT2 GPIO0_64
0x1104 PADCONFIG_65 F5 MMC1_DAT1 GPIO0_65
0x1108 PADCONFIG_66 H3 MMC1_DAT0 GPIO0_66
0x110C PADCONFIG_67 J4 MMC1_CLK GPIO0_67
0x1110 PADCONFIG_68 J2 MMC1_CMD GPIO0_68
0x1114 PADCONFIG_69 J3 MMC1_SDCD GPIO0_69
0x1118 PADCONFIG_70 K3 MMC1_SDWP GPIO0_70
0x111C PADCONFIG_71 K2 MMC1_POW GPIO0_71
0x1120 PADCONFIG_72 A22 MII_RXCLK RGMII_RXC GPIO0_72
0x1124 PADCONFIG_73 A23 PR0_EDIO_DATA3 GPIO0_73 eHRPWM3_A
0x1128 PADCONFIG_74 B22 PR0_EDIO_DATA2 GPIO0_74 eHRPWM3_B
0x112C PADCONFIG_75 C22 PR0_EDIO_DATA1 GPIO0_75 eHRPWM3_SYNCI
0x1130 PADCONFIG_76 D23 PR0_EDIO_DATA0 GPIO0_76 eHRPWM3_SYNCO
0x1134 PADCONFIG_77 F22 MII_RXD3 RGMII_RXD3 GPIO0_77
0x1138 PADCONFIG_78 B23 MII_RXD2 RGMII_RXD2 GPIO0_78
0x113C PADCONFIG_79 C23 MII_RXD1 RGMII_RXD1 RMII_RXD1 GPIO0_79
0x1140 PADCONFIG_80 B24 MII_RXD0 RGMII_RXD0 RMII_RXD0 GPIO0_80
0x1144 PADCONFIG_81 A24 MII_RXDV RGMII_RXCTL GPIO0_81
0x1148 PADCONFIG_82 F23 MII_RXER RMII_RXER GPIO0_82
0x114C PADCONFIG_83 B25 MII_COL GPIO0_83
0x1150 PADCONFIG_84 G22 MII_CRS RMII_CRS_DV GPIO0_84
0x1154 PADCONFIG_85 C25 MII_TXCLK RGMII_TXC GPIO0_85
0x1158 PADCONFIG_86 C24 SPI3_SCSn0 PR0_eCAP0_eCAP_CAPIN_APWM_O GPIO0_86
0x115C PADCONFIG_87 E25 SPI3_SCSn1 PR0_UART0_RXD GPIO0_87
0x1160 PADCONFIG_88 E24 SPI3_CLK PR0_UART0_TXD GPIO0_88
0x1164 PADCONFIG_89 F25 SPI3_SOMI PR0_UART0_CTSN GPIO0_89
0x1168 PADCONFIG_90 F24 SPI3_SIMO PR0_UART0_RTSN GPIO0_90
0x116C PADCONFIG_91 D25 MII_TXD3 RGMII_TXD3 GPIO0_91
0x1170 PADCONFIG_92 G25 MII_TXD2 RGMII_TXD2 GPIO0_92
0x1174 PADCONFIG_93 G24 MII_TXD1 RGMII_TXD1 RMII_TXD1 GPIO0_93
0x1178 PADCONFIG_94 G23 MII_TXD0 RGMII_TXD0 RMII_TXD0 GPIO0_94
0x117C PADCONFIG_95 H25 MII_TXEN RGMII_TXCTL RMII_TXEN GPIO0_95
0x1180 PADCONFIG_96 H24 MII_TXER PR0_eCAP0_eCAP_SYNCIN GPIO0_96 eHRPWM_TZn3
0x1184 PADCONFIG_97 D24 RMII_REFCLK PR0_eCAP0_eCAP_SYNCOUT
0x1188 PADCONFIG_98 V3 MDIO_DATA GPIO0_97
0x118C PADCONFIG_99 U3 MDIO_CLK GPIO0_98
0x1190 PADCONFIG_100 M3 SPI0_SCSn0
0x1194 PADCONFIG_101 M4 SPI0_SCSn1 GPIO0_99
0x1198 PADCONFIG_102 M2 SPI0_CLK
0x119C PADCONFIG_103 M1 SPI0_SOMI
0x11A0 PADCONFIG_104 N4 SPI0_SIMO
0x11A4 PADCONFIG_105 P1 SPI1_SCSn0
0x11A8 PADCONFIG_106 N3 SPI1_SCSn1 GPIO0_100
0x11AC PADCONFIG_107 N2 SPI1_CLK
0x11B0 PADCONFIG_108 N1 SPI1_SOMI
0x11B4 PADCONFIG_109 P2 SPI1_SIMO
0x11B8 PADCONFIG_110 P3 SPI2_SCSn0 GPIO0_101
0x11BC PADCONFIG_111 P4 SPI2_SCSn1 GPIO0_102
0x11C0 PADCONFIG_112 R2 SPI2_CLK GPIO0_103
0x11C4 PADCONFIG_113 R4 SPI2_SOMI GPIO0_104
0x11C8 PADCONFIG_114 R3 SPI2_SIMO GPIO0_105
0x11CC PADCONFIG_115 T4 UART0_RXD
0x11D0 PADCONFIG_116 T1 UART0_TXD
0x11D4 PADCONFIG_117 T2 UART0_CTSn TIMI0 GPIO0_106
0x11D8 PADCONFIG_118 U1 UART0_RTSn TIMO0 GPIO0_107
0x11DC PADCONFIG_119 T3 UART1_RXD GPIO1_48
0x11E0 PADCONFIG_120 T5 UART1_TXD GPIO1_49
0x11E4 PADCONFIG_121 U2 UART1_CTSn GPIO1_50
0x11E8 PADCONFIG_122 U4 UART1_RTSn GPIO1_51
0x11EC PADCONFIG_123 E21 UART2_RXD PR1_EDIO_DATA3 UART0_DCDn GPIO1_52 CPTS_HW1_TSPUSH
0x11F0 PADCONFIG_124 D21 UART2_TXD PR1_EDIO_DATA2 UART0_DSRn GPIO1_53 CPTS_HW2_TSPUSH
0x11F4 PADCONFIG_125 D22 UART2_CTSn PR1_EDIO_DATA1 UART0_DTRn GPIO1_54 CPTS_TS_SYNC
0x11F8 PADCONFIG_126 C21 UART2_RTSn PR1_EDIO_DATA0 UART0_RIN GPIO1_55 CPTS_TS_COMP
0x11FC PADCONFIG_127 P5 DCAN0_TX GPIO1_56
0x1200 PADCONFIG_128 R5 DCAN0_RX GPIO1_57
0x1204 PADCONFIG_129 K25 QSPI_CLK GPIO1_58
0x1208 PADCONFIG_130 K24 QSPI_RCLK GPIO1_59
0x120C PADCONFIG_131 J23 QSPI_D0 GPIO1_60
0x1210 PADCONFIG_132 J22 QSPI_D1 GPIO1_61
0x1214 PADCONFIG_133 J21 QSPI_D2 GPIO1_62
0x1218 PADCONFIG_134 J24 QSPI_D3 GPIO1_63
0x121C PADCONFIG_135 J25 QSPI_CSn0 GPIO1_64
0x1220 PADCONFIG_136 H23 QSPI_CSn1 CLKOUT GPIO1_65
0x1224 PADCONFIG_137 H22 QSPI_CSn2 DCAN1_TX PR1_UART0_CTSN GPIO1_66 USB0_EXT_TRIGGER
0x1228 PADCONFIG_138 H21 QSPI_CSn3 DCAN1_RX PR1_UART0_RTSN GPIO1_67 USB1_EXT_TRIGGER
0x122C PADCONFIG_139 D3 PR0_PRU0_GPO0 PR0_PRU0_GPI0 GPIO0_108 MCASP2_AXR0
0x1230 PADCONFIG_140 A2 PR0_PRU0_GPO1 PR0_PRU0_GPI1 GPIO0_109 MCASP2_AXR1
0x1234 PADCONFIG_141 E4 PR0_PRU0_GPO2 PR0_PRU0_GPI2 GPIO0_110 MCASP2_AXR2
0x1238 PADCONFIG_142 B1 PR0_PRU0_GPO3 PR0_PRU0_GPI3 GPIO0_111 MCASP2_AXR3
0x123C PADCONFIG_143 A3 PR0_PRU0_GPO4 PR0_PRU0_GPI4 GPIO0_112 MCASP2_AXR4
0x1240 PADCONFIG_144 E5 PR0_PRU0_GPO5 PR0_PRU0_GPI5 GPIO0_113 MCASP2_AXR5
0x1244 PADCONFIG_145 B2 PR0_PRU0_GPO6 PR0_PRU0_GPI6 GPIO0_114 MCASP2_ACLKR
0x1248 PADCONFIG_146 D4 PR0_PRU0_GPO7 PR0_PRU0_GPI7 GPIO0_115 MCASP2_AFSR
0x124C PADCONFIG_147 E6 PR0_PRU0_GPO8 PR0_PRU0_GPI8 GPIO0_116 MCASP2_AHCLKR
0x1250 PADCONFIG_148 C2 PR0_PRU0_GPO9 PR0_PRU0_GPI9 XREFCLK GPIO0_117 MCASP2_AMUTE
0x1254 PADCONFIG_149 C3 PR0_PRU0_GPO10 PR0_PRU0_GPI10 GPIO0_118 MCASP2_AFSX
0x1258 PADCONFIG_150 D5 PR0_PRU0_GPO11 PR0_PRU0_GPI11 GPIO0_119 MCASP2_AHCLKX
0x125C PADCONFIG_151 B3 PR0_PRU0_GPO12 PR0_PRU0_GPI12 GPIO0_120 MCASP2_ACLKX
0x1260 PADCONFIG_152 B4 PR0_PRU0_GPO13 PR0_PRU0_GPI13 GPIO0_121 MCASP1_ACLKR
0x1264 PADCONFIG_153 A4 PR0_PRU0_GPO14 PR0_PRU0_GPI14 GPIO0_122 MCASP1_AFSR
0x1268 PADCONFIG_154 E7 PR0_PRU0_GPO15 PR0_PRU0_GPI15 GPIO0_123 MCASP1_AHCLKR
0x126C PADCONFIG_155 D6 PR0_PRU0_GPO16 PR0_PRU0_GPI16 GPIO0_124 MCASP1_ACLKX
0x1270 PADCONFIG_156 C4 PR0_PRU0_GPO17 PR0_PRU0_GPI17 PR1_UART0_RXD GPIO0_125 MCASP1_AFSX
0x1274 PADCONFIG_157 C5 PR0_PRU0_GPO18 PR0_PRU0_GPI18 PR0_EDC_LATCH0_IN GPIO0_126 MCASP1_AHCLKX
0x1278 PADCONFIG_158 A5 PR0_PRU0_GPO19 PR0_PRU0_GPI19 PR0_EDC_SYNC0_OUT GPIO0_127 MCASP1_AMUTE
0x127C PADCONFIG_159 B5 PR0_PRU1_GPO0 PR0_PRU1_GPI0 GPIO0_128 MCASP1_AXR0
0x1280 PADCONFIG_160 B6 PR0_PRU1_GPO1 PR0_PRU1_GPI1 GPIO0_129 MCASP1_AXR1
0x1284 PADCONFIG_161 D7 PR0_PRU1_GPO2 PR0_PRU1_GPI2 GPIO0_130 MCASP1_AXR2
0x1288 PADCONFIG_162 A6 PR0_PRU1_GPO3 PR0_PRU1_GPI3 GPIO0_131 MCASP1_AXR3
0x128C PADCONFIG_163 C6 PR0_PRU1_GPO4 PR0_PRU1_GPI4 GPIO0_132 MCASP1_AXR4
0x1290 PADCONFIG_164 E8 PR0_PRU1_GPO5 PR0_PRU1_GPI5 GPIO0_133 MCASP1_AXR5
0x1294 PADCONFIG_165 A7 PR0_PRU1_GPO6 PR0_PRU1_GPI6 GPIO0_134 MCASP1_AXR6
0x1298 PADCONFIG_166 D8 PR0_PRU1_GPO7 PR0_PRU1_GPI7 GPIO0_135 MCASP1_AXR7
0x129C PADCONFIG_167 F9 PR0_PRU1_GPO8 PR0_PRU1_GPI8 GPIO0_136 MCASP1_AXR8
0x12A0 PADCONFIG_168 B7 PR0_PRU1_GPO9 PR0_PRU1_GPI9 GPIO0_137 MCASP1_AXR9
0x12A4 PADCONFIG_169 C7 PR0_PRU1_GPO10 PR0_PRU1_GPI10 GPIO0_138 MCASP0_AMUTE
0x12A8 PADCONFIG_170 E9 PR0_PRU1_GPO11 PR0_PRU1_GPI11 GPIO0_139 MCASP0_ACLKR
0x12AC PADCONFIG_171 A8 PR0_PRU1_GPO12 PR0_PRU1_GPI12 GPIO0_140 MCASP0_AFSR
0x12B0 PADCONFIG_172 B8 PR0_PRU1_GPO13 PR0_PRU1_GPI13 GPIO0_141 MCASP0_AHCLKR
0x12B4 PADCONFIG_173 D9 PR0_PRU1_GPO14 PR0_PRU1_GPI14 GPIO0_142 MCASP0_ACLKX
0x12B8 PADCONFIG_174 C8 PR0_PRU1_GPO15 PR0_PRU1_GPI15 GPIO0_143 MCASP0_AFSX
0x12BC PADCONFIG_175 C9 PR0_PRU1_GPO16 PR0_PRU1_GPI16 GPIO1_00 MCASP0_AHCLKX
0x12C0 PADCONFIG_176 B9 PR0_PRU1_GPO17 PR0_PRU1_GPI17 PR1_UART0_TXD GPIO1_01 MCASP0_AXR0
0x12C4 PADCONFIG_177 A9 PR0_PRU1_GPO18 PR0_PRU1_GPI18 PR0_EDC_LATCH1_IN GPIO1_02 MCASP0_AXR1
0x12C8 PADCONFIG_178 B10 PR0_PRU1_GPO19 PR0_PRU1_GPI19 PR0_EDC_SYNC1_OUT GPIO1_03 MCASP0_AXR2
0x12CC PADCONFIG_179 A10 PR0_MDIO_DATA GPIO1_04 MCASP0_AXR3
0x12D0 PADCONFIG_180 C10 PR0_MDIO_MDCLK GPIO1_05 MCASP0_AXR4
0x12D4 PADCONFIG_181 E10 PR1_PRU0_GPO0 PR1_PRU0_GPI0 GPIO1_06 MCASP0_AXR5
0x12D8 PADCONFIG_182 D10 PR1_PRU0_GPO1 PR1_PRU0_GPI1 GPIO1_07 MCASP0_AXR6
0x12DC PADCONFIG_183 F10 PR1_PRU0_GPO2 PR1_PRU0_GPI2 GPIO1_08 MCASP0_AXR7
0x12E0 PADCONFIG_184 C11 PR1_PRU0_GPO3 PR1_PRU0_GPI3 GPIO1_09 MCASP0_AXR8
0x12E4 PADCONFIG_185 D11 PR1_PRU0_GPO4 PR1_PRU0_GPI4 MMC0_POW GPIO1_10 MCASP0_AXR9
0x12E8 PADCONFIG_186 E11 PR1_PRU0_GPO5 PR1_PRU0_GPI5 MMC0_SDWP GPIO1_11 MCASP0_AXR10
0x12EC PADCONFIG_187 F12 PR1_PRU0_GPO6 PR1_PRU0_GPI6 MMC0_SDCD GPIO1_12 MCASP0_AXR11
0x12F0 PADCONFIG_188 E12 PR1_PRU0_GPO7 PR1_PRU0_GPI7 MMC0_DAT7 GPIO1_13 MCASP0_AXR12
0x12F4 PADCONFIG_189 C12 PR1_PRU0_GPO8 PR1_PRU0_GPI8 MMC0_DAT6 GPIO1_14 MCASP0_AXR13
0x12F8 PADCONFIG_190 B11 PR1_PRU0_GPO9 PR1_PRU0_GPI9 MMC0_DAT5 GPIO1_15 MCASP0_AXR14
0x12FC PADCONFIG_191 B12 PR1_PRU0_GPO10 PR1_PRU0_GPI10 MMC0_DAT4 GPIO1_16 MCASP0_AXR15
0x1300 PADCONFIG_192 A12 PR1_PRU0_GPO11 PR1_PRU0_GPI11 MMC0_DAT3 GPIO1_17
0x1304 PADCONFIG_193 A11 PR1_PRU0_GPO12 PR1_PRU0_GPI12 MMC0_DAT2 GPIO1_18
0x1308 PADCONFIG_194 A13 PR1_PRU0_GPO13 PR1_PRU0_GPI13 MMC0_DAT1 GPIO1_19
0x130C PADCONFIG_195 B13 PR1_PRU0_GPO14 PR1_PRU0_GPI14 MMC0_DAT0 GPIO1_20
0x1310 PADCONFIG_196 F13 PR1_PRU0_GPO15 PR1_PRU0_GPI15 MMC0_CLK GPIO1_21
0x1314 PADCONFIG_197 C13 PR1_PRU0_GPO16 PR1_PRU0_GPI16 MMC0_CMD GPIO1_22
0x1318 PADCONFIG_198 E13 PR1_PRU0_GPO17 PR1_PRU0_GPI17 GPIO1_23 eHRPWM_TZn4 eHRPWM_SOCA
0x131C PADCONFIG_199 D12 PR1_PRU0_GPO18 PR1_PRU0_GPI18 PR1_EDC_LATCH0_IN GPIO1_24 eHRPWM4_A
0x1320 PADCONFIG_200 D13 PR1_PRU0_GPO19 PR1_PRU0_GPI19 PR1_EDC_SYNC0_OUT GPIO1_25 eHRPWM4_B
0x1324 PADCONFIG_201 A14 PR1_PRU1_GPO0 PR1_PRU1_GPI0 GPIO1_26
0x1328 PADCONFIG_202 B14 PR1_PRU1_GPO1 PR1_PRU1_GPI1 GPIO1_27
0x132C PADCONFIG_203 C14 PR1_PRU1_GPO2 PR1_PRU1_GPI2 GPIO1_28
0x1330 PADCONFIG_204 E14 PR1_PRU1_GPO3 PR1_PRU1_GPI3 GPIO1_29
0x1334 PADCONFIG_205 D14 PR1_PRU1_GPO4 PR1_PRU1_GPI4 GPIO1_30
0x1338 PADCONFIG_206 A15 PR1_PRU1_GPO5 PR1_PRU1_GPI5 GPIO1_31
0x133C PADCONFIG_207 F14 PR1_PRU1_GPO6 PR1_PRU1_GPI6 GPIO1_32
0x1340 PADCONFIG_208 B15 PR1_PRU1_GPO7 PR1_PRU1_GPI7 GPIO1_33
0x1344 PADCONFIG_209 C15 PR1_PRU1_GPO8 PR1_PRU1_GPI8 GPIO1_34
0x1348 PADCONFIG_210 D15 PR1_PRU1_GPO9 PR1_PRU1_GPI9 MCBSP_DR GPIO1_35
0x134C PADCONFIG_211 A16 PR1_PRU1_GPO10 PR1_PRU1_GPI10 MCBSP_DX GPIO1_36
0x1350 PADCONFIG_212 E15 PR1_PRU1_GPO11 PR1_PRU1_GPI11 MCBSP_FSX GPIO1_37
0x1354 PADCONFIG_213 B16 PR1_PRU1_GPO12 PR1_PRU1_GPI12 MCBSP_CLKX GPIO1_38
0x1358 PADCONFIG_214 C16 PR1_PRU1_GPO13 PR1_PRU1_GPI13 MCBSP_FSR GPIO1_39
0x135C PADCONFIG_215 D17 PR1_PRU1_GPO14 PR1_PRU1_GPI14 MCBSP_CLKR GPIO1_40
0x1360 PADCONFIG_216 C18 PR1_PRU1_GPO15 PR1_PRU1_GPI15 GPIO1_41
0x1364 PADCONFIG_217 D16 PR1_PRU1_GPO16 PR1_PRU1_GPI16 GPIO1_42
0x1368 PADCONFIG_218 F16 PR1_PRU1_GPO17 PR1_PRU1_GPI17 GPIO1_43 eHRPWM_TZn5 eHRPWM_SOCB
0x136C PADCONFIG_219 E17 PR1_PRU1_GPO18 PR1_PRU1_GPI18 PR1_EDC_LATCH1_IN GPIO1_44 eHRPWM5_A
0x1370 PADCONFIG_220 E16 PR1_PRU1_GPO19 PR1_PRU1_GPI19 PR1_EDC_SYNC1_OUT GPIO1_45 eHRPWM5_B
0x1374 PADCONFIG_221 E18 PR1_MDIO_DATA GPIO1_46 eCAP0_IN_APWM0_OUT
0x1378 PADCONFIG_222 D18 PR1_MDIO_MDCLK GPIO1_47 eCAP1_IN_APWM1_OUT
0x1394 PADCONFIG_229 W1 NMIn
0x1398 PADCONFIG_230 V2 LRESETn
0x139C PADCONFIG_231 V1 LRESETNMIENn
0x13AC PADCONFIG_235 Y2 RESETSTATn
0x13B0 PADCONFIG_236 Y3 BOOTCOMPLETE
0x13B4 PADCONFIG_237 M21 SYSCLKOUT
0x13B8 PADCONFIG_238 N5 OBSPLL_LOCK
0x1408 PADCONFIG_258 E19 USB0_DRVVBUS
0x140C PADCONFIG_259 B21 USB1_DRVVBUS