SPRS866G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Enhancements in KeyStone II
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
    7. 6.7 C66x CorePac Register Descriptions
  7. ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
            2. 10.1.2.2.2.2 I2C Master Mode
          3. 10.1.2.2.3 SPI Boot Device Configuration
          4. 10.1.2.2.4 EMIF Boot Device Configuration
          5. 10.1.2.2.5 NAND Boot Device Configuration
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. 10.1.2.4.1 PCIe Boot Device Configuration
          2. 10.1.2.4.2 HyperLink Boot Device Configuration
          3. 10.1.2.4.3 UART Boot Device Configuration
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
        2. 10.2.3.2  Device Configuration Register
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
        27. 10.2.3.27 SYNECLK_PINCTL Register
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
        9. 11.5.2.9 Reset Isolation Register (RSISO)
      3. 11.5.3 Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
    12. 11.12 HyperLink Peripheral
    13. 11.13 UART Peripheral
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

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メカニカル・データ(パッケージ|ピン)
  • AAW|1517
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発注情報

66AK2Hxx Peripheral Information

This chapter covers the various peripherals on the 66AK2Hxx device. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.

Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the 66AK2Hxx. The various power supply rails and their primary functions are listed in Table 11-1.

Table 11-1 Power Supply Rails on the 66AK2Hxx

Name Primary Function Voltage Notes
AVDDAx Core PLL, DDR3 DLL supply voltage 1.8 V Core PLL, DDR3 DLL supply
CVDD SmartReflex DSP core supply voltage 0.8 – 1.1 V DSP variable core supply
CVDD1 DSP core fixed supply voltage 0.95 V DSP Core fixed supply
CVDDT1 ARM core fixed supply voltage 0.95 V ARM core fixed supply
DVDD15 DDR3A, DDR3B I/O power supply voltage 1.35 V / 1.5 V DDR3A, DDR3B I/O power supply
DVDD18 1.8-V I/O power supply voltage 1.8 V 1.8-V I/O power supply
DVDD33 USB 3.3-V IO supply 3.3 V USB high voltage supply
VDDAHV SerDes I/O power supply voltage 1.8 V SerDes I/O power supply
VDDALV SerDes analog power supply voltage 0.85 V SerDes analog supply
VDDUSB USB LV PHY power supply voltage 0.85 V USB LV PHY supply
VP, VPTX Filtered 0.85-V supply voltage 0.85 V Filtered 0.85-V USB supply
VSS Ground GND Ground

Power-Up Sequencing

This section defines the requirements for a power-up sequencing from a power-on reset condition. There are two acceptable power sequences for the device.

The first sequence stipulates the core voltages starting before the IO voltages as shown below.

  1. CVDD
  2. CVDD1, CVDDT1, VDDAHV, AVDDAx, DVDD18
  3. DVDD15
  4. VDDALV, VDDUSB, VP, VPTX
  5. DVDD33

The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.

  1. VDDAHV, AVDDAx, DVDD18
  2. CVDD
  3. CVDD1, CVDDT1
  4. DVDD15
  5. VDDALV, VDDUSB, VP, VPTX
  6. DVDD33

The clock input buffers for SYSCLK, ARMCLK, ALTCORECLK, DDR3ACLK, DDR3BCLK, PASSCLK, and SRIOSGMIICLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDD is present.

If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled to ground through a 1-kΩ resistor. The P leg should be tied to CVDD to ensure it will not have any voltage present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device.

The device initialization is divided into two phases. The first phase consists of the time period from the activation of the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire power stabilization phase.

This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL triggers the end of the initialization phase, but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock that is used by the CorePacs. See Figure 11-7 for more details.

Core-Before-IO Power Sequencing

The details of the Core-before-IO power sequencing are defined in Table 11-2. Figure 11-1 shows power sequencing and reset control of the 66AK2Hxx. POR may be removed after the power has been stable for the required 100 µsec. RESETFULL must be held low for a period (see item 9 in Figure 11-1) after the rising edge of POR, but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed.

NOTE

TI recommends a maximum of 80 ms between one power rail being valid and the next power rail in the sequence starting to ramp.

Table 11-2 Core-Before-IO Power Sequencing

ITEM SYSTEM STATE
1 Begin Power Stabilization Phase
  • CVDD (core AVS) ramps up.
  • POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR) is put into the reset state.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a
  • CVDD1 and CVDDT1 (core constant) ramps at the same time or within 80 ms of CVDD. Although ramping CVDD1 simultaneously with CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
  • The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
  • The timing for CVDD1 is based on CVDD valid. CVDD1 and DVDD18/ADDAVH/AVDDAx may be enabled at the same time but do not need to ramp simultaneously. CVDD1 may be valid before or after DVDD18/ADDAVH/AVDDAx are valid, as long as the timing above is met.
2b
  • VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD. DVDD18 must be enabled within 80 ms of CVDD valid and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100 ms from the time when CVDD is valid to the time when DVDD18 is valid.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
  • The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD valid. DVDD18/ADDAVH/AVDDAx and CVDD1and CVDDT1 may be enabled at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after CVDD1 and CVDDT1 are valid, as long as the timing above is met.
2c
  • Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.
2d
  • The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by item 7.
3
  • DVDD15 can ramp up within 80ms of when DVDD18 is valid.
  • RESETSTAT is driven low once the DVDD18 supply is available.
  • All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
  • RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high.
4
  • VDDALV, VDDUSB, VP and VPTX ramp up within 80ms of when DVDD15 is valid.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
  • DVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSB, VP and VPTX are valid.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6
  • POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
7
  • Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
8
  • RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
9
  • The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin.
  • Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles.
End device initialization phase
10
  • GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
11
  • GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
66AK2H14 66AK2H12 66AK2H06 Core_Before_IO_Power_Seq_with_ARM.gif Figure 11-1 Core-Before-IO Power Sequencing

IO-Before-Core Power Sequencing

The timing diagram for IO-before-core power sequencing is shown in Figure 11-2 and defined in Table 11-3.

NOTE

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.

Table 11-3 IO-Before-Core Power Sequencing

ITEM SYSTEM STATE
1 Begin Power Stabilization Phase
  • VDDAHV, AVDDAx and DVDD18 ramp up.
  • POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR ) is put into the reset state.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2
  • CVDD (core AVS) ramps within 80 ms from the time ADDAHV, AVDDAx and DVDD18 are valid.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a
  • RESET may be driven high any time after DVDD18 is at a valid level. must be high before POR is driven high.
3
  • CVDD1 and CVDDT1 (core constant) ramp at the same time or within 80 ms following CVDD. Although ramping CVDD1and CVDDT1 simultaneously with CVDD is permitted, the voltage for CVDD1 and CVDDT1 must never exceed CVDD until after CVDD has reached a valid voltage.
  • The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 and CVDDT1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 and CVDDT1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1 and CVDDT1.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
  • Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state.
3b
  • The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by item 8.
4
  • DVDD15 can ramp up within 80 ms of when CVDD1 is valid.
  • RESETSTAT is driven low once the DVDD18 supply is available.
  • All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
  • VDDALV, VDDUSB, VP and VPTX should ramp up within 80 ms of when DVDD15 is valid.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6
  • DVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSB, VP and VPTX are valid.
  • Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
7
  • POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
8
  • Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
9
  • RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
10
  • The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
  • Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles.
End device initialization phase
11
  • GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
12
  • GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
66AK2H14 66AK2H12 66AK2H06 IO_Before_Core_Power_Seq_with_ARM.gif Figure 11-2 IO-Before-Core Power Sequencing

Prolonged Resets

Holding the device in POR, RESETFULL, or RESET for long periods of time may affect the long-term reliability of the part (due to an elevated voltage condition that can stress the part). The device should not be held in a reset for times exceeding one hour at a time and no more than 5% of the total lifetime for which the device is powered-up. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the device to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.

Clocking During Power Sequencing

Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the clocks is contingent on the state of the boot configuration pins. Table 11-4 describes the clock sequencing and the conditions that affect clock operation. All clock drivers should be in a high-impedance state until CVDD is at a valid level and that all clock inputs be either active or in a static state with one leg pulled to ground and the other connected to CVDD.

Table 11-4 Clock Sequencing

CLOCK CONDITION SEQUENCING
DDR3ACLK None Must be present 16 µsec before POR transitions high.
DDR3BCLK None Must be present 16 µsec before POR transitions high.
SYSCLK CORECLKSEL = 0 SYSCLK is used to clock the core PLL. It must be present 16 µsec before POR transitions high.
CORECLKSEL = 1 Reserved.
ALTCORECLK CORECLKSEL = 0 ALTCORECLK is not used and should be tied to a static state.
CORECLKSEL = 1 ALTCORECLK is used to clock the core PLL. It must be present 16 µsec before POR transitions high.
PASSCLK PASSCLKSEL = 0 PASSCLK is not used and should be tied to a static state.
PASSCLKSEL = 1 PASSCLK is used as a source for the PASS PLL. It must be present before the PASS PLL is removed from reset and programmed.
SRIOSGMIICLK An SGMII port will be used. SRIOSGMIICLK must be present 16 µsec before POR transitions high.
SGMII will not be used. SRIO will be used as a boot device. SRIOSGMIICLK must be present 16 µsec before POR transitions high.
SGMII will not be used. SRIO will be used after boot. SRIOSGMIICLK is used as a source to the SRIO SerDes PLL. It must be present before the SRIO is removed from reset and programmed.
SGMII will not be used. SRIO will not be used. SRIOSGMIICLK is not used and should be tied to a static state.
PCIECLK PCIE will be used as a boot device. PCIECLK must be present 16 µsec before POR transitions high.
PCIE will be used after boot. PCIECLK is used as a source to the PCIE SerDes PLL. It must be present before the PCIe is removed from reset and programmed.
PCIE will not be used. PCIECLK is not used and should be tied to a static state.
HYPCLK HyperLink will be used as a boot device. HYPCLK must be present 16 µsec before POR transitions high.
HyperLink will be used after boot. HYPCLK is used as a source to the HyperLink SerDes PLL. It must be present before the HyperLink is removed from reset and programmed.
HyperLink will not be used. HYPCLK is not used and should be tied to a static state.

Power-Down Sequence

The power-down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent an excessive amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can affect long term reliability.

Power Supply Decoupling and Bulk Capacitor

To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of power supply decoupling and bulk capacitors see Hardware Design Guide for KeyStone II Devices.

SmartReflex

Increasing the device complexity increases its power consumption. With higher clock rates and increased performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in any powered circuit, independent of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, which is the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.

Texas Instruments SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the 66AK2Hxx device is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each 66AK2Hxx device.

To help maximize performance and minimize power consumption of the device, SmartReflex is required to be implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins (depending on power supply device being used), which are used to select the output voltage of the core voltage regulator.

For information on implementation of SmartReflex, see Power Consumption Summary for KeyStone TCI66x Devices and Hardware Design Guide for KeyStone II Devices.

SmartReflex switching characteristics are shown in Table 11-5.

Table 11-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics

(see Figure 11-3)
NO. PARAMETER MIN MAX UNIT
1 td(VCNTL[4:2]-VCNTL[5]) Delay time – VCNTL[4:2] valid after VCNTL[5] low 300.00 ns
2 toh(VCNTL[5]-VCNTL[4:2]) Output hold time – VCNTL[4:2] valid after VCNTL[5] 0.07 172020C(1) ms
3 td(VCNTL[4:2]-VCNTL[5]) Delay time – VCNTL[4:2] valid after VCNTL[5] high 300.00 ns
4 toh(VCNTL[5]-VCNTL[2:0) Output hold time – VCNTL[4:2] valid after VCNTL[5] high 0.07 172020C ms
C = 1/SYSCLK1 frequency, in ms (see Figure 11-9)
66AK2H14 66AK2H12 66AK2H06 SmartReflex_4-Pin_VID_Interface_Timing_NySh.gif Figure 11-3 SmartReflex 4-Pin 6-Bit VID Interface Timing

Power Sleep Controller (PSC)

The Power Sleep Controller (PSC) includes a Global Power Sleep Controller (GPSC) and a number of Local Power Sleep Controllers (LPSC) that control overall device power by turning off unused power domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several important power and clock operations.

For information on the Power Sleep Controller, see the KeyStone Architecture Power Sleep Controller (PSC) User's Guide.

Power Domains

The device has several power domains that can be turned on for operation or off to minimize power dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various power domains.

Table 11-6 shows the 66AK2Hxx power domains.

Table 11-6 66AK2Hx Power Domains

DOMAIN BLOCK(S) NOTE POWER CONNECTION
0 Most peripheral logic (BOOTCFG, EMIF16, I2C, INTC, GPIO, USB) Cannot be disabled Always on
1 Per-core TETB and system TETB RAMs can be powered down Software control
2 Network Coprocessor Logic can be powered down Software control
3 PCIe Logic can be powered down Software control
4 SRIO Logic can be powered down Software control
5 HyperLink0 Logic can be powered down Software control
6 Reserved
7 MSMC RAM MSMC RAM can be powered down Software control
8 C66x Core 0, L1/L2 RAMs L2 RAMs can sleep Software control via C66x CorePac. For details, see the TMS320C66x DSP CorePac User's Guide.
9 C66x Core 1, L1/L2 RAMs L2 RAMs can sleep
10 C66x Core 2, L1/L2 RAMs L2 RAMs can sleep
11 C66x Core 3, L1/L2 RAMs L2 RAMs can sleep
12 C66x Core 4, L1/L2 RAMs (66AK2H12/14 only) L2 RAMs can sleep
13 C66x Core 5, L1/L2 RAMs (66AK2H12/14 only) L2 RAMs can sleep
14 C66x Core 6, L1/L2 RAMs (66AK2H12/14 only) L2 RAMs can sleep
15 C66x Core 7, L1/L2 RAMs (66AK2H12/14 only) L2 RAMs can sleep
16 EMIF(DDR3A, DDR3B) Logic can be powered down Software control
17 Reserved
18 Reserved
19 Reserved
20 Reserved
21 Reserved
22 Reserved
23 Reserved
24 Reserved
25 Reserved
26 Reserved
27 Reserved
28 HyperLink1 Logic can be powered down Software control
29 10GbE (66AK2H14 only) Logic can be powered down Software control
30 ARM Smart Reflex Logic can be powered down Software control
31 ARM CorePac Logic can be powered down Software control

Clock Domains

Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable the clocks of that module at the source. For modules that share a clock with other modules, the LPSC controls the clock gating logic for each module.

Table 11-7 shows the 66AK2Hxx clock domains.

Table 11-7 Clock Domains

LPSC NUMBER MODULE(S) NOTES
0 Shared LPSC for all peripherals other than those listed in this table Always on
1 Reserved
2 USB Software control
3 EMIF16 and SPI Software control
4 Reserved
5 Debug subsystem and tracers Software control
6 Reserved Always on
7 Packet Accelerator Software control
8 Ethernet SGMIIs Software control
9 Security Accelerator Software control
10 PCIe Software control
11 SRIO Software control
12 HyperLink0 Software control
13 SmartReflex Always on
14 MSMC RAM Software control
15 C66x CorePac0 Always on
16 C66x CorePac1 Software control
17 C66x CorePac2 Software control
18 C66x CorePac3 Software control
19 C66x CorePac4 (66AK2H12/14 only) Software control
20 C66x CorePac5 (66AK2H12/14 only) Software control
21 C66x CorePac6 (66AK2H12/14 only) Software control
22 C66x CorePac7 (66AK2H12/14 only) Software control
23 DDR3A EMIF Software control
24 DDR3B EMIF Software control
25 Reserved
26 Reserved
27 Reserved
28 Reserved
29 Reserved
30 Reserved
31 Reserved
32 Reserved
33 Reserved
34 Reserved
35 Reserved
36 Reserved
37 Reserved
38 Reserved
39 Reserved
40 Reserved
41 Reserved
42 Reserved
43 Reserved
44 Reserved
45 Reserved
46 Reserved
47 Reserved
48 Reserved
49 Hyperlink1 Software control
50 10GbE (66AK2H14 only) Software control
51 ARM Smart Reflex Software control
52 ARM CorePac Software control
No LPSC Bootcfg, PSC, and PLL Controller These modules do not use LPSC

PSC Register Memory Map

Table 11-8 shows the PSC Register memory map.

Table 11-8 PSC Register Memory Map

OFFSET REGISTER DESCRIPTION
0x000 PID Peripheral Identification Register
0x004 – 0x010 Reserved Reserved
0x014 VCNTLID Voltage Control Identification Register
0x018 – 0x11C Reserved Reserved
0x120 PTCMD Power Domain Transition Command Register
0x124 Reserved Reserved
0x128 PTSTAT Power Domain Transition Status Register
0x12C – 0x1FC Reserved Reserved
0x200 PDSTAT0 Power Domain Status Register 0
0x204 PDSTAT1 Power Domain Status Register 1
0x208 PDSTAT2 Power Domain Status Register 2
0x20C PDSTAT3 Power Domain Status Register 3
0x210 PDSTAT4 Power Domain Status Register 4
0x214 PDSTAT5 Power Domain Status Register 5
0x218 PDSTAT6 Power Domain Status Register 6
0x21C PDSTAT7 Power Domain Status Register 7
0x220 PDSTAT8 Power Domain Status Register 8
0x224 PDSTAT9 Power Domain Status Register 9
0x228 PDSTAT10 Power Domain Status Register 10
0x22C PDSTAT11 Power Domain Status Register 11
0x230 PDSTAT12 Power Domain Status Register 12
0x234 PDSTAT13 Power Domain Status Register 13
0x238 PDSTAT14 Power Domain Status Register 14
0x23C PDSTAT15 Power Domain Status Register 15
0x240 PDSTAT16 Power Domain Status Register 16
0x244 PDSTAT17 Power Domain Status Register 17
0x248 PDSTAT18 Power Domain Status Register 18
0x24C PDSTAT19 Power Domain Status Register 19
0x250 PDSTAT20 Power Domain Status Register 20
0x254 PDSTAT21 Power Domain Status Register 21
0x258 PDSTAT22 Power Domain Status Register 22
0x25C PDSTAT23 Power Domain Status Register 23
0x260 PDSTAT24 Power Domain Status Register 24
0x264 PDSTAT25 Power Domain Status Register 25
0x268 PDSTAT26 Power Domain Status Register 26
0x26C PDSTAT27 Power Domain Status Register 27
0x270 PDSTAT28 Power Domain Status Register 28
0x274 PDSTAT29 Power Domain Status Register 29
0x278 PDSTAT30 Power Domain Status Register 30
0x27C PDSTAT31 Power Domain Status Register 31
0x27C – 0x2FC Reserved Reserved
0x300 PDCTL0 Power Domain Control Register 0
0x304 PDCTL1 Power Domain Control Register 1
0x308 PDCTL2 Power Domain Control Register 2
0x30C PDCTL3 Power Domain Control Register 3
0x310 PDCTL4 Power Domain Control Register 4
0x314 PDCTL5 Power Domain Control Register 5
0x318 PDCTL6 Power Domain Control Register 6
0x31C PDCTL7 Power Domain Control Register 7
0x320 PDCTL8 Power Domain Control Register 8
0x324 PDCTL9 Power Domain Control Register 9
0x328 PDCTL10 Power Domain Control Register 10
0x32C PDCTL11 Power Domain Control Register 11
0x330 PDCTL12 Power Domain Control Register 12
0x334 PDCTL13 Power Domain Control Register 13
0x338 PDCTL14 Power Domain Control Register 14
0x33C PDCTL15 Power Domain Control Register 15
0x340 PDCTL16 Power Domain Control Register 16
0x344 PDCTL17 Power Domain Control Register 17
0x348 PDCTL18 Power Domain Control Register 18
0x34C PDCTL19 Power Domain Control Register 19
0x350 PDCTL20 Power Domain Control Register 20
0x354 PDCTL21 Power Domain Control Register 21
0x358 PDCTL22 Power Domain Control Register 22
0x35c PDCTL23 Power Domain Control Register 23
0x360 PDCTL24 Power Domain Control Register 24
0x364 PDCTL25 Power Domain Control Register 25
0x368 PDCTL26 Power Domain Control Register 26
0x36C PDCTL27 Power Domain Control Register 27
0x370 PDCTL28 Power Domain Control Register 28
0x374 PDCTL29 Power Domain Control Register 29
0x378 PDCTL30 Power Domain Control Register 30
0x37C PDCTL31 Power Domain Control Register 31
0x380 – 0x7FC Reserved Reserved
0x800 MDSTAT0 Module Status Register 0 (never gated)
0x804 MDSTAT1 Module Status Register 1
0x808 MDSTAT2 Module Status Register 2
0x80C MDSTAT3 Module Status Register 3
0x810 MDSTAT4 Module Status Register 4
0x814 MDSTAT5 Module Status Register 5
0x818 MDSTAT6 Module Status Register 6
0x81C MDSTAT7 Module Status Register 7
0x820 MDSTAT8 Module Status Register 8
0x824 MDSTAT9 Module Status Register 9
0x828 MDSTAT10 Module Status Register 10
0x82C MDSTAT11 Module Status Register 11
0x830 MDSTAT12 Module Status Register 12
0x834 MDSTAT13 Module Status Register 13
0x838 MDSTAT14 Module Status Register 14
0x83C MDSTAT15 Module Status Register 15
0x840 MDSTAT16 Module Status Register 16
0x844 MDSTAT17 Module Status Register 17
0x848 MDSTAT18 Module Status Register 18
0x84C MDSTAT19 Module Status Register 19
0x850 MDSTAT20 Module Status Register 20
0x854 MDSTAT21 Module Status Register 21
0x858 MDSTAT22 Module Status Register 22
0x85C MDSTAT23 Module Status Register 23
0x860 MDSTAT24 Module Status Register 24
0x864 MDSTAT25 Module Status Register 25
0x868 MDSTAT26 Module Status Register 26
0x86C MDSTAT27 Module Status Register 27
0x870 MDSTAT28 Module Status Register 28
0x874 MDSTAT29 Module Status Register 29
0x878 MDSTAT30 Module Status Register 30
0x87C MDSTAT31 Module Status Register31
0x880 MDSTAT32 Module Status Register 32
0x884 MDSTAT33 Module Status Register 33
0x888 MDSTAT34 Module Status Register 34
0x88C MDSTAT35 Module Status Register 35
0x890 MDSTAT36 Module Status Register 36
0x894 MDSTAT37 Module Status Register 37
0x898 MDSTAT38 Module Status Register 38
0x89C MDSTAT39 Module Status Register 39
0x8A0 MDSTAT40 Module Status Register 40
0x8A4 MDSTAT41 Module Status Register 41
0x8A8 MDSTAT42 Module Status Register 42
0x8AC MDSTAT43 Module Status Register 43
0x8B0 MDSTAT44 Module Status Register 44
0x8B4 MDSTAT45 Module Status Register 45
0x8B8 MDSTAT46 Module Status Register 46
0x8BC MDSTAT47 Module Status Register 47
0x8C0 MDSTAT48 Module Status Register 48
0x8C4 MDSTAT49 Module Status Register 49
0x8C8 MDSTAT50 Module Status Register 50
0x8CC MDSTAT51 Module Status Register 51
0x8D0 MDSTAT52 Module Status Register 52
0x8D4 – 0x9FC Reserved Reserved
0xA00 MDCTL0 Module Control Register 0 (never gated)
0xA04 MDCTL1 Module Control Register 1
0xA08 MDCTL2 Module Control Register 2
0xA0C MDCTL3 Module Control Register 3
0xA10 MDCTL4 Module Control Register 4
0xA14 MDCTL5 Module Control Register 5
0xA18 MDCTL6 Module Control Register 6
0xA1C MDCTL7 Module Control Register 7
0xA20 MDCTL8 Module Control Register 8
0xA24 MDCTL9 Module Control Register 9
0xA28 MDCTL10 Module Control Register 10
0xA2C MDCTL11 Module Control Register 11
0xA30 MDCTL12 Module Control Register 12
0xA34 MDCTL13 Module Control Register 13
0xA38 MDCTL14 Module Control Register 14
0xA3C MDCTL15 Module Control Register 15
0xA40 MDCTL16 Module Control Register 16
0xA44 MDCTL17 Module Control Register 17
0xA48 MDCTL18 Module Control Register 18
0xA4C MDCTL19 Module Control Register 19
0xA50 MDCTL20 Module Control Register 20
0xA54 MDCTL21 Module Control Register 21
0xA58 MDCTL22 Module Control Register 22
0xA5C MDCTL23 Module Control Register 23
0xA60 MDCTL24 Module Control Register 24
0xA64 MDCTL25 Module Control Register 25
0xA68 MDCTL26 Module Control Register 26
0xA6C MDCTL27 Module Control Register 27
0xA70 MDCTL28 Module Control Register 28
0xA74 MDCTL29 Module Control Register 29
0xA78 MDCTL30 Module Control Register 30
0xA7C MDCTL31 Module Control Register31
0xA80 MDCTL32 Module Control Register 32
0xA84 MDCTL33 Module Control Register 33
0xA88 MDCTL34 Module Control Register 34
0xA8C MDCTL35 Module Control Register 35
0xA90 MDCTL36 Module Control Register 36
0xA94 MDCTL37 Module Control Register 37
0xA98 MDCTL38 Module Control Register 38
0xA9C MDCTL39 Module Control Register 39
0xAA0 MDCTL40 Module Control Register 40
0xAA4 MDCTL41 Module Control Register 41
0xAA8 MDCTL42 Module Control Register 42
0xAAC MDCTL43 Module Control Register 43
0xAB0 MDCTL44 Module Control Register 44
0xAB4 MDCTL45 Module Control Register 45
0xAB8 MDCTL46 Module Control Register 46
0xABC MDCTL47 Module Control Register 47
0xAC0 MDCTL48 Module Control Register 48
0xAC4 MDCTL49 Module Control Register 49
0xAC8 MDCTL50 Module Control Register 50
0xACC MDCTL51 Module Control Register 51
0xAD0 MDCTL52 Module Control Register 52
0xAD4 – 0xFFC Reserved Reserved

Reset Controller

The reset controller detects the different type of resets supported on the 66AK2Hxx device and manages the distribution of those resets throughout the device. The device has the following types of resets:

  • Power-on reset
  • Hard reset
  • Soft reset
  • Local reset

Table 11-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more information on the effects of each reset on the PLL controllers and their clocks, see Section 11.4.8.

Table 11-9 Reset Types

TYPE INITIATOR EFFECT(S)
Power-on reset POR pin Resets the entire chip including the test and emulation logic. The device configuration pins are latched only during power-on reset.
RESETFULL pin
Hard reset RESET pin Hard reset resets everything except for test, emulation logic, and reset isolation modules. This reset is different from power-on reset in that the PLL Controller assumes power and clocks are stable when a hard reset is asserted. The device configurations pins are not relatched.

Emulation-initiated reset is always a hard reset.

By default, these initiators are configured as hard reset, but can be configured (except emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in self-refresh mode.

PLLCTL Register (RSCTRL)(1)
Watchdog timers
Emulation
Soft reset RESET pin Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and DDR3 EMIF MMRs contents are retained.

By default, these initiators are configured as hard reset, but can be configured as soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained during a soft reset if the SDRAM is placed in self-refresh mode.

PLLCTL Register (RSCTRL)
Watchdog timers
Local reset LRESET pin Resets the C66x CorePac, without disturbing clock alignment or memory contents. The device configuration pins are not relatched.
Watchdog timer time-out
LPSC MMRs
All masters in the device have access to the PLL control registers.

Power-on Reset

Power-on reset is used to reset the entire device, including the test and emulation logic.

Power-on reset is initiated by the following:

  1. POR pin
  2. RESETFULL pin

During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device, including the reset-isolated logic, when the device is already powered up. For this reason, the RESETFULL pin, unlike POR, should be driven by the onboard host control other than the power good circuitry. For power-on reset, the Core PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.

The following sequence must be followed during a power-on reset:

  1. Wait for all power supplies to reach normal operating conditions while keeping the POR and RESETFULL pins asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and remain in their reset state until otherwise configured by their respective peripheral. All peripherals that are power-managed are disabled after a power-on reset and must be enabled through the Device State Control Registers (for more details, see Section 10.2.3).
  2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in reset.
  3. POR must be held active until all supplies on the board are stable, and then for at least an additional period of time (as specified in Section 11.2.1) for the chip-level PLLs to lock.
  4. The POR pin can now be deasserted. Reset-sampled pin values are latched at this point. Then, all chip-level PLLs are taken out of reset, locking sequences begin, and all power-on device initialization processes begin.
  5. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time, the DDR3A PLL and DDR3B PLL have already completed their locking sequences and are supplying a valid clock. The system clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide-by settings.
  6. The device is now out of reset and code execution begins as dictated by the selected boot mode.

NOTE

To most of the device, reset is deasserted only when the POR and RESET pins are both deasserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The RESET pin should not be tied to the POR pin.

Hard Reset

A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-isolated modules. POR should also remain deasserted during this time.

Hard reset is initiated by the following:

  • RESET pin
  • RSCTRL Register in the PLL Controller
  • Watchdog timer
  • Emulation

By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft resets.

The following sequence must be followed during a hard reset:

  1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time, the RESET signal propagates to all modules (except those specifically mentioned above). To prevent off-chip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
  2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
  3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not relatched and clocking is unaffected within the device.
  4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high).

NOTE

The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied to the POR pin.

Soft Reset

A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3A EMIF MMRs, PCIe MMRs sticky bits, and external memory content are retained. POR should also remain deasserted during this time.

Soft reset is initiated by the following:

  • RESET pin
  • RSCTRL Register in the PLL Controller
  • Watchdog timer

In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3A and DDR3B memory controller registers are not reset. If the user places the DDR3A and DDR3B SDRAM in self-refresh mode before invoking the soft reset, the DDR3A and DDR3B SDRAM memory content is retained.

During a soft reset, the following occurs:

  1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates through the system. Internal system clocks are not affected. PLLs remain locked.
  2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL Controller pauses system clocks for approximately eight cycles. At this point:
    • The peripherals remain in the state they were in before the soft reset.
    • The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT Register.
    • The DDR3A and DDR3B MMRs and PCIe MMRs retain their previous values. Only the DDR3A and DDR3B memory controller and PCIe state machines are reset by the soft reset.
    • The PLL Controller remains in the mode it was in before the soft reset.
    • System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration pins are not latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used to select the boot mode.

Local Reset

The local reset can be used to reset a particular C66x CorePac without resetting any other device components.

Local reset is initiated by the following:

  • LRESET pin
  • Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG registers in the PLL Controller. (See Section 11.5.2.8 and Section 8.3.2.)
    • Local reset
    • NMI
    • NMI followed by a time delay and then a local reset for the C66x CorePac selected
    • Hard reset by requesting reset via the PLL Controller
  • LPSC MMRs (memory-mapped registers)

For more details see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

ARM CorePac Reset

The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such as the Cortex-A15 processor, memory subsystem, debug logic, and so forth. The ARM CorePac incorporates the PSC to generate resets for its internal modules. Details of reset generation and distribution inside the ARM CorePac can be found in the KeyStone II Architecture ARM CorePac User's Guide.

Reset Priority

If any of the previously mentioned reset sources occur simultaneously, the PLL Controller processes only the highest priority reset request. The reset request priorities are as follows (high to low):

  • Power-on reset
  • Hard/soft reset

Reset Controller Register

The reset controller registers are part of the PLL Controller MMRs. All 66AK2Hxx device-specific MMRs are covered in Section 11.5.2. For more details on these registers and how to program them, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

Reset Electrical Data and Timing

Table 11-10 shows the reset timing requirements and Table 11-11 shows the reset switching characteristics.

Table 11-10 Reset Timing Requirements(1)

(see Figure 11-4 and Figure 11-5)
NO. MIN MAX UNIT
RESETFULL Pin Reset
1 tw(RESETFULL) Pulse width – pulse width RESETFULL low 500C ns
Soft/Hard-Reset
2 tw(RESET) Pulse width – pulse width RESET low 500C ns
C = 1/SYSCLK1 clock frequency in ns

Table 11-11 Reset Switching Characteristics(1)

(see Figure 11-4 and Figure 11-5)
NO. PARAMETER MIN MAX UNIT
RESETFULL Pin Reset
3 td(RESETFULLH-RESETSTATH) Delay time – RESETSTAT high after RESETFULL high 50000C ns
Soft/Hard Reset
4 td(RESETH-RESETSTATH) Delay time – RESETSTAT high after RESET high 50000C ns
C = 1/SYSCLK1 clock frequency in ns
66AK2H14 66AK2H12 66AK2H06 Resetfull_Reset_Timing.gif Figure 11-4 RESETFULL Reset Timing
66AK2H14 66AK2H12 66AK2H06 Soft-Hard_Reset_Timing.gif Figure 11-5 Soft/Hard Reset Timing

Table 11-12 shows the boot configuration timing requirements.

Table 11-12 Boot Configuration Timing Requirements(1)

(see Figure 11-6)
NO. MIN MAX UNIT
1 tsu(GPIOn-RESETFULL) Setup time – GPIO valid before RESETFULL asserted 12C ns
2 th(RESETFULL-GPIOn) Hold time – GPIO valid after RESETFULL asserted 12C ns
C = 1/SYSCLK1 clock frequency in ns.
66AK2H14 66AK2H12 66AK2H06 Boot_Config_Timing_NySh.gif Figure 11-6 Boot Configuration Timing

Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers

This section provides a description of the Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL, and the PLL Controller. For details on the operation of the PLL Controller module, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

The Main PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios, alignment, and gating for the system clocks to the device. By default, the device powers up with the main PLL bypassed. Figure 11-7 shows a block diagram of the Main PLL and the PLL Controller.

The ARM PLL, DDR3A PLL, DDR3B PLL, and PASS PLL are used to provide dedicated clock to the ARM CorePac, DDR3A, DDR3B, and PASS respectively. These chip level PLLs support a wide range of multiplier and divider values, which can be programmed through the chip level registers in the Device Control register block. The Boot ROM will program the multiplier values for main PLL, ARM PLL and PASS PLL based on boot mode. (See Section 10 for more details.)

The DDR3A PLL and DDR3B PLL are used to supply clocks to DDR3A and DDR3B EMIF logic. These PLLs can also be used without programming the PLL Controller. Instead, they can be controlled using the chip-level registers (DDR3APLLCTL0, DDR3APLLCTL1, DDR3BPLLCTL0, DDR3BPLLCTL1) in the Device Control register block. To write to these registers, software must go through an unlocking sequence using the KICK0/KICK1 registers.

The multiplier values for all chip-level PLLs can be reprogrammed later based on the input parameter table. This feature provides flexibility in that these PLLs may be able to reuse other clock sources instead of having its own clock source.

66AK2H14 66AK2H12 66AK2H06 Main_PLL_and_PLL_Controller_66AK2Hxx.gif Figure 11-7 Main PLL and PLL Controller

The Main PLL Controller registers can be accessed by any master in the device. The PLLM[5:0] bits of the multiplier are controlled by the PLLM Register inside the PLL Controller and the PLLM[12:6] bits are controlled by the chip-level MAINPLLCTL0 Register. The output divide and bypass logic of the PLL are controlled by fields in the SECCTL Register in the PLL Controller. Only PLLDIV3, and PLLDIV4 are programmable on the device. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide for more details on how to program the PLL controller.

The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the Main PLL Controller. The Main PLL Controller also controls reset propagation through the chip, clock alignment, and test points. The Main PLL Controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See Hardware Design Guide for KeyStone II Devices for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see Section 11.5.5.

It should be assumed that any registers not included in these sections are not supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

The PLL Controller module as described in the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide includes a superset of features, some of which are not supported on the 66AK2Hxx device. The following sections describe the registers that are supported.

Main PLL Controller Device-Specific Information

Internal Clocks and Maximum Operating Frequencies

The Main PLL, used to drive the C66x CorePacs, the switch fabric, and a majority of the peripheral clocks (all but theARM CorePacs, DDR3, and the PASS modules) requires a PLL Controller to manage the various clock divisions, gating, and synchronization. Unlike other PLL, CLKOD functionality of Main PLL is replaced by PLL controller Post-Divider register (POSTDIV). The POSTDIV.RATIO[3:0] and POSTDIV.POSTDEN bits control the post divider ratio and divider enable respectively. PLLM[5:0] input of the Main PLL is controlled by the PLL controller PLLM register.

The Main PLL Controller has four SYSCLK outputs that are listed below, along with the clock descriptions. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.

  • SYSCLK1: Full-rate clock for all C66x CorePacs. Using local dividers, SYSCLK1 is used to derive clocks required for the majority of peripherals that do not need reset isolation.
  • The system peripherals and modules driven by SYSCLK1 are as follows; however, not all peripherals are supported in every part. See the Features chapter for the complete list of peripherals supported in your part.

    EMIF16, USB 3.0, HyperLink, PCIe, SGMII, SRIO, GPIO, Timer64, I2C, SPI, TeraNet, UART, ROM, CIC, Security Manager, BootCFG, PSC, Queue Manager, Semaphore, MPUs, EDMA, MSMC, DDR3, EMIF.

  • SYSCLK2: Full-rate, reset-isolated clock used to generate various other clocks required by peripherals that need reset isolation: for example, SmartReflex and SRIO.
  • SYSCLK3: 1/x-rate clock used to clock the C66x CorePac emulation. The default rate for this clock is 1/3. This clock is programmable from /1 to /32, where this clock does not violate the maximum of 350 MHz. SYSCLK3 can be turned off by software.
  • SYSCLK4: 1/z-rate clock for the system trace module only. The default rate for this clock is 1/5. This clock is configurable: the maximum configurable clock is 210 MHz and the minimum configuration clock is 32 MHz. SYSCLK4 can be turned off by software.
  • SYSCLK5: Slow, free running clock. The default rate for this clock is 1/24. SYSCLK5 cannot be turned off by software.

Only SYSCLK3, SYSCLK4, and SYSCLK5 are programmable.

Local Clock Dividers

The clock signals from the Main PLL Controller are routed to various modules and peripherals on the device. Some modules and peripherals have one or more internal clock dividers. Other modules and peripherals have no internal clock dividers, but are grouped together and receive clock signals from a shared local clock divider. Internal and shared local clock dividers have fixed division ratios, as shown in Table 11-13.

Table 11-13 Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers

CLOCK MODULE INTERNAL CLOCK DIVIDER(S) SHARED LOCAL CLOCK DIVIDER
SYSCLK1 Internal Clock Dividers
SYSCLK1 ARM CorePac /1, /3, /3, /6, /6 --
C66x DSP CorePacs /1, /2, /3, /4 --
Chip Interrupt Controllers (CICx) /6 --
DDR3 Memory Controller A (also receives clocks from the DDR3A_PLL) /2 --
DDR3 Memory Controller B (also receives clocks from the DDR3B_PLL) /3 --
EMIF16 /6 --
HyperLink /2, /3, /6 --
MultiCore Shared Memory Controller (MSMC) /1 --
PCI express (PCIe) /2, /3, /4, /6 --
ROM /6 --
Serial Gigabit Media Independent Interface (SGMII) /2, /3, /6, /8 --
Universal Asynchronous Receiver/Transmitter (UART) /6 --
Universal Serial Bus 3.0 (USB 3.0) /3, /6 --
SYSCLK1 Shared Local Clock Dividers
SYSCLK1 Power/Sleep Controller (PSC) -- /12, /24
EDMA -- /3
Memory Protection Units (MPUx)
Semaphore
TeraNet (SYSCLK1/3 domain)
SYSCLK1 Boot Config -- /6
General-Purpose Input/Output (GPIO)
I2C
Security Manager
Serial Peripheral Interconnect (SPI)
TeraNet (CPU /6 domain)
Timers
SYSCLK2 Internal Clock Dividers
SYSCLK2 Serial RapidIO (SRIO) /3, /4, /6 --
SmartReflex C66x CorePacs /12, /128 --
SmartReflex ARM CorePac /12, /128, /128 --

Module Clock Input

Table 11-7 lists various clock domains in the device and their distribution in each peripheral. The table also shows the distributed clock division in modules and their mapping with source clocks of the device PLLs.

Main PLL Controller Operating Modes

The Main PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the BYPASS bit of the PLL Secondary Control Register (SECCTL).

  • In bypass mode, PLL input is fed directly out as SYSCLK1.
  • In PLL mode, SYSCLK1 is generated from the PLL output using the values set in the PLLM and PLLD fields in the MAINPLLCTL0 Register.

External hosts must avoid access attempts to the DSP while the frequency of its internal clocks is changing. User software must implement a mechanism that causes the DSP to notify the host when the PLL configuration has completed.

Main PLL Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device power-up. The device should not be taken out of reset until this stabilization time has elapsed.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value, see Table 11-14.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the PLL Controller can be switched to PLL mode. The Main PLL lock time is given in Table 11-14 .

Table 11-14 Main PLL Stabilization, Lock, and Reset Times

PARAMETER MIN TYP MAX UNIT
PLL stabilization time 100 µs
PLL lock time 2000 × C (1)
PLL reset time 1000 ns
C = SYSCLK1(N|P) cycle time in ns.

PLL Controller Memory Map

The memory map of the Main PLL controller is shown in Table 11-15. 66AK2Hxx-specific Main PLL controller register definitions can be found in the sections following Table 11-15. For other registers in the table, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

It is recommended to use read-modify-write sequence to make any changes to the valid bits in the Main PLL controller registers.

Note that only registers documented here are accessible on the 66AK2Hxx. Other addresses in the Main PLL controller memory map including the Reserved registers must not be modified. Furthermore, only the bits within the registers described here are supported.

Table 11-15 PLL Controller Registers (Including Reset Controller)

HEX ADDRESS RANGE ACRONYM REGISTER NAME
00 0231 0000 – 00 0231 00E3 - Reserved
00 0231 00E4 RSTYPE Reset Type Status Register (Reset Main PLL Controller)
00 0231 00E8 RSTCTRL Software Reset Control Register (Reset Main PLL Controller)
00 0231 00EC RSTCFG Reset Configuration Register (Reset Main PLL Controller)
00 0231 00F0 RSISO Reset Isolation Register (Reset Main PLL Controller)
00 0231 00F0 – 00 0231 00FF - Reserved
00 0231 0100 PLLCTL PLL Control Register
00 0231 0104 - Reserved
00 0231 0108 SECCTL PLL Secondary Control Register
00 0231 010C - Reserved
00 0231 0110 PLLM PLL Multiplier Control Register
00 0231 0114 - Reserved
00 0231 0118 PLLDIV1 PLL Controller Divider 1 Register
00 0231 011C PLLDIV2 PLL Controller Divider 2 Register
00 0231 0120 PLLDIV3 PLL Controller Divider 3 Register
00 0231 0124 - Reserved
00 0231 0128 POSTDIV PLL Controller Post-Divide Register
00 0231 012C – 00 0231 0134 - Reserved
00 0231 0138 PLLCMD PLL Controller Command Register
00 0231 013C PLLSTAT PLL Controller Status Register
00 0231 0140 ALNCTL PLL Controller Clock Align Control Register
00 0231 0144 DCHANGE PLLDIV Ratio Change Status Register
00 0231 0148 CKEN Reserved
00 0231 014C CKSTAT Reserved
00 0231 0150 SYSTAT SYSCLK Status Register
00 0231 0154 – 00 0231 015C - Reserved
00 0231 0160 PLLDIV4 PLL Controller Divider 4 Register
00 0231 0164 PLLDIV5 Reserved
00 0231 0168 PLLDIV6 Reserved
00 0231 016C PLLDIV7 Reserved
00 0231 0170 PLLDIV8 Reserved
00 0231 0174 – 00 0231 0193 PLLDIV9 – PLLDIV16 Reserved
00 0231 0194 – 00 0231 01FF - Reserved

PLL Secondary Control Register (SECCTL)

The PLL secondary control register contains extra fields to control the Main PLL and is shown in Figure 11-8 and described in Table 11-16.

Figure 11-8 PLL Secondary Control Register (SECCTL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved BYPASS OUTPUT DIVIDE Reserved
R-0000 0000 RW-1 RW-0001 RW-001 0000 0000 0000 0000
Legend: R/W = Read/Write; R = Read only; – n = value after reset

Table 11-16 PLL Secondary Control Register Field Descriptions

Bit Field Description
31-24 Reserved Reserved
23 BYPASS PLL bypass mode:
  • 0 = PLL is not in BYPASS mode
  • 1 = PLL is in BYPASS mode
22-19 OUTPUT DIVIDE Output divider ratio bits
  • 0h = ÷1. Divide frequency by 1
  • 1h = ÷2. Divide frequency by 2
  • 2h = ÷3. Divide frequency by 3
  • 3h = ÷4. Divide frequency by 4
  • 4h – Fh = ÷5 to ÷16. Divide frequency range: divide frequency by 5 to divide frequency by 80.
18-0 Reserved Reserved

PLL Controller Divider Register (PLLDIV3 and PLLDIV4)

The PLL controller divider registers (PLLDIV3 and PLLDIV4) are shown in Figure 11-9 and described in Table 11-17. The default values of the RATIO field on a reset for PLLDIV3, and PLLDIV4 are different as mentioned in the footnote of Figure 11-9 .

Figure 11-9 PLL Controller Divider Register (PLLDIVn)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Dn(1)EN Reserved RATIO
R-0 R/W-1 R-0 R/W-n(2)
Legend: R/W = Read/Write; R = Read only; – n = value after reset
D3EN for PLLDIV3; D4EN for PLLDIV4
n=02h for PLLDIV3; n=03h for PLLDIV4

Table 11-17 PLL Controller Divider Register Field Descriptions

Bit Field Description
31-16 Reserved Reserved
15 DnEN Divider Dn enable bit (See footnote of Figure 11-9 )
  • 0 = Divider n is disabled
  • 1 = No clock output. Divider n is enabled.
14-8 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0 RATIO Divider ratio bits (See footnote of Figure 11-9 )
  • 0h = ÷1. Divide frequency by 1
  • 1h = ÷2. Divide frequency by 2
  • 2h = ÷3. Divide frequency by 3
  • 3h = ÷4. Divide frequency by 4
  • 4h – 4Fh = ÷5 to ÷80. Divide frequency range: divide frequency by 5 to divide frequency by 80.

PLL Controller Clock Align Control Register (ALNCTL)

The PLL controller clock align control register (ALNCTL) is shown in Figure 11-10 and described in Table 11-18.

Figure 11-10 PLL Controller Clock Align Control Register (ALNCTL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ALN4 ALN3 Reserved
R-0 R/W-1 R/W-1 R-0
Legend: R/W = Read/Write; R = Read only; – n = value after reset, for reset value

Table 11-18 PLL Controller Clock Align Control Register Field Descriptions

Bit Field Description
31-5 Reserved Reserved. This location is always read as 0. A value written to this field has no effect.
4-3 ALN[4:3] SYSCLKn alignment. Do not change the default values of these fields.
  • 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
  • 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
2-0 Reserved Reserved. This location is always read as 0. A value written to this field has no effect.

PLLDIV Divider Ratio Change Status Register (DCHANGE)

Whenever a different ratio is written to the PLLDIVn registers, the PLL CTL flags the change in the DCHANGE status register. During the GO operation, the PLL controller changes only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other clocks. The PLLDIV divider ratio change status register is shown in Figure 11-11 and described in Table 11-19.

Figure 11-11 PLLDIV Divider Ratio Change Status Register (DCHANGE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SYS4 SYS3 Reserved
R-0 R/W-1 R/W-1 R-0
Legend: R/W = Read/Write; R = Read only; – n = value after reset, for reset value

Table 11-19 PLLDIV Divider Ratio Change Status Register Field Descriptions

Bit Field Description
31-5 Reserved Reserved. This bit location is always read as 0. A value written to this field has no effect.
4-3 SYS[4:3] Identifies when the SYSCLKn divide ratio has been modified.
  • 0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
  • 1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
2-0 Reserved Reserved. This bit location is always read as 0. A value written to this field has no effect.

SYSCLK Status Register (SYSTAT)

The SYSCLK status register (SYSTAT) shows the status of SYSCLK[4:1]. SYSTAT is shown in Figure 11-12 and described in Table 11-20.

Figure 11-12 SYSCLK Status Register (SYSTAT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SYS4ON SYS3ON SYS2ON SYS1ON
R-n R-1 R-1 R-1 R-1
Legend: R/W = Read/Write; R = Read only; – n = value after reset

Table 11-20 SYSCLK Status Register Field Descriptions

Bit Field Description
31-4 Reserved Reserved. This location is always read as 0. A value written to this field has no effect.
3-0 SYS[N]ON(1) SYSCLK[N] on status
  • 0 = SYSCLK[N] is gated
  • 1 = SYSCLK[N] is on
Where N = 1, 2, 3, or 4

Reset Type Status Register (RSTYPE)

The reset type status register (RSTYPE) latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The reset type status register is shown in Figure 11-13 and described in Table 11-21.

Figure 11-13 Reset Type Status Register (RSTYPE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved EMU-RST Reserved WDRST[N] Reserved PLLCTRLRST RESET POR
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Legend: R = Read only; – n = value after reset

Table 11-21 Reset Type Status Register Field Descriptions

Bit Field Description
31-29 Reserved Reserved. Always reads as 0. Writes have no effect.
28 EMU-RST Reset initiated by emulation
  • 0 = Not the last reset to occur
  • 1 = The last reset to occur
27-12 Reserved Reserved. Always reads as 0. Writes have no effect.
11-8 WDRST[3:0] Reset initiated by Watchdog Timer[N]
  • 0 = Not the last reset to occur
  • 1 = The last reset to occur
7-3 Reserved Reserved. Always reads as 0. Writes have no effect.
2 PLLCTLRST Reset initiated by PLLCTL
  • 0 = Not the last reset to occur
  • 1 = The last reset to occur
1 RESET RESET reset
  • 0 = RESET was not the last reset to occur
  • 1 = RESET was the last reset to occur
0 POR Power-on reset
  • 0 = Power-on reset was not the last reset to occur
  • 1 = Power-on reset was the last reset to occur

Reset Control Register (RSTCTRL)

This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value is 0x5A69. A valid key will be stored as 0x000C. Any other key value is invalid. When the RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key. The software reset control register (RSTCTRL) is shown in Figure 11-14 and described in Table 11-22.

Figure 11-14 Reset Control Register (RSTCTRL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SWRST KEY
R-0x0000 R/W-0x(1) R/W-0x0003
Legend: R = Read only; – n = value after reset;
Writes are conditional based on valid key.

Table 11-22 Reset Control Register Field Descriptions

Bit Field Description
31-17 Reserved Reserved
16 SWRST Software reset
  • 0 = Reset
  • 1 = Not reset
15-0 KEY Key used to enable writes to RSTCTRL and RSTCFG.

Reset Configuration Register (RSTCFG)

This register is used to configure the type of reset (a hard reset or a soft reset) initiated by RESET, the watchdog timer, and the RSTCTRL register of the Main PLL controller. By default, these resets are hard resets. The RSTCFG is shown in Figure 11-15 and described in Table 11-23.

Figure 11-15 Reset Configuration Register (RSTCFG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0x000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PLLCTLRSTTYPE RESET TYPE Reserved WDTYPE[N](1)
R-0x000000 R/W-0(2) R/W-0(2) R-0x0 R/W-0x00(2)
Legend: R = Read only; R/W = Read/Write; – n = value after reset
Where N = 1, 2, 3,....N (Not all these outputs may be used on a specific device.)
Writes are conditional based on valid key. For details, see Section 11.5.2.7.

Table 11-23 Reset Configuration Register Field Descriptions

Bit Field Description
31-14 Reserved Reserved
13 PLLCTLRSTTYPE PLL controller initiates a software-driven reset of type:
  • 0 = Hard reset (default)
  • 1 = Soft reset
12 RESET TYPE RESET initiates a reset of type:
  • 0 = Hard reset (default)
  • 1 = Soft reset
11-4 Reserved Reserved
3-0 WDTYPE[3:0] Watchdog timer [N] initiates a reset of type:
  • 0 = Hard reset (default)
  • 1 = Soft reset

Reset Isolation Register (RSISO)

This register is used to select the module clocks that must maintain their clocking without pausing through nonpower-on reset. Setting any of these bits effectively blocks reset to all Main PLL control registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the module-specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-isolate a particular module. For more information on the MDCTLx register, see the KeyStone Architecture Power Sleep Controller (PSC) User's Guide. The RSISO is shown in Figure 11-16 and described in Table 11-24.

Figure 11-16 Reset Isolation Register (RSISO)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved SRIOISO SRISO Reserved Rsvd Reserved
R-0x0000 R-0x00 R/W-0 R/W-0 R-0x0 R/W-0 R-000
Legend: R = Read only; R/W = Read/Write; – n = value after reset

Table 11-24 Reset Isolation Register Field Descriptions

Bit Field Description
31-10 Reserved Reserved.
9 SRIOISO Isolate SRIO module control
  • 0 = Not reset isolated
  • 1 = Reset isolated
8 SRISO Isolate SmartReflex control
  • 0 = Not reset isolated
  • 1 = Reset isolated
7-4 Reserved Reserved
3 Reserved Reserved
2-0 Reserved Reserved

Main PLL Control Registers

The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the Main PLL controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.

For valid configurable values of the MAINPLLCTL registers, see Section 10.1.4. See Section 10.2.3.4 for the address location of the KICK registers and their locking and unlocking sequences.

See Figure 11-17 and Table 11-25 for MAINPLLCTL0 details and Figure 11-18 and Table 11-26 for MAINPLLCTL1 details.

Figure 11-17 Main PLL Control Register 0 (MAINPLLCTL0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWADJ[7:0] Reserved PLLM[12:6] Reserved PLLD
RW-0000 0101 RW – 0000 0 RW-0000000 RW-000000 RW-000000
Legend: RW = Read/Write; – n = value after reset

Table 11-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions

Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.
23-19 Reserved Reserved
18-12 PLLM[12:6] 7-bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor minus 1.

The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the PLLM[12:6] bits are controlled by the above chip-level register. MAINPLLCTL0 register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL Controller. See the Section 11.5.2.1 for more details.

11-6 Reserved Reserved
5-0 PLLD A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
Figure 11-18 Main PLL Control Register 1 (MAINPLLCTL1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ENSAT Reserved BWADJ[11:8]
RW-0000000000000000000000000 RW-0 R-00 RW- 0000
Legend: RW = Read/Write; – n = value after reset

Table 11-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions

Bit Field Description
31-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper PLL operation
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.

ARM PLL Control Registers

The ARM PLL uses two chip-level registers (ARMPLLCTL0 and ARMPLLCTL1) without using the Main PLL controller like other PLLs for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.

For valid configurable values of the ARMPLLCTL registers, see Section 10.1.4. See Section 10.2.3.4 for the address location of the KICK registers and their locking and unlocking sequences.

See Figure 11-19 and Table 11-27 for ARMPLLCTL0 details and Figure 11-20 and Table 11-28 for ARMPLLCTL1 details.

Figure 11-19 ARM PLL Control Register 0 (ARMPLLCTL0)(1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWADJ[7:0] BYPASS CLKOD PLLM PLLD
RW-0000 1001 RW-1 RW-0001 RW-0000000010011 RW-000000
Legend: RW = Read/Write; – n = value after reset
This register is Reset on POR only. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.

Table 11-27 ARM PLL Control Register 0 Field Descriptions

Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.
23 BYPASS PLL bypass mode:
  • 0 = PLL is not in BYPASS mode
  • 1 = PLL is in BYPASS mode
22-19 CLKOD A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1
18-6 PLLM A 13-bit field that selects the values for the multiplication factor
5-0 PLLD A 6-bit field that selects the values for the reference divider
Figure 11-20 ARM PLL Control Register 1 (ARMPLLCTL1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PLLRST Reserved ENSAT Reserved BWADJ[11:8]
RW-00000000000000000 RW-0 RW-0000000 RW-0 R-00 RW-0000
Legend: RW = Read/Write; – n = value after reset

Table 11-28 ARM PLL Control Register 1 Field Descriptions

Bit Field Description
31-15 Reserved Reserved
14 PLLRST PLL Reset bit
  • 0 = PLL Reset is released
  • 1 = PLL Reset is asserted
13-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper PLL operation
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.

See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the ARM PLL is also controlled by the SECCTL register in the PLL Controller. See Section 11.5.2.1 for more details.

Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing

The Main PLL controller, ARM, SRIO, HyperLink, PCIe, USB clock input timing requirements are shown in Table 11-29.

Table 11-29 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Timing Requirements(1)

(see Figure 11-21, Figure 11-22, Figure 11-23 and Figure 11-24)
NO. MIN MAX UNIT
SYSCLK[P:N]
1 tc(SYSCLKN) Cycle time SYSCLKN cycle time 3.25 25 ns
1 tc(SYSCLKP) Cycle time SYSCLKP cycle time 3.25 25 ns
3 tw(SYSCLKN) Pulse width SYSCLKN high 0.45*tc 0.55*tc ns
2 tw(SYSCLKN) Pulse width SYSCLKN low 0.45*tc 0.55*tc ns
2 tw(SYSCLKP) Pulse width SYSCLKP high 0.45*tc 0.55*tc ns
3 tw(SYSCLKP) Pulse width SYSCLKP low 0.45*tc 0.55*tc ns
4 tr(SYSCLK_200 mV) Transition time SYSCLK differential rise time (200 mV) 50 350 ps
4 tf(SYSCLK_200 mV) Transition time SYSCLK differential fall time (200 mV) 50 350 ps
5 tj(SYSCLKN) Jitter, peak_to_peak _ periodic SYSCLKN 0.2*tc(SYSCLKN) ps
5 tj(SYSCLKP) Jitter, peak_to_peak _ periodic SYSCLKP 0.2*tc(SYSCLKP) ps
ARMCLK[P:N]
1 tc(ARMCLKN) Cycle time ARMCLKN cycle time 3.2 25 ns
1 tc(ARMCLKP) Cycle time ARMCLKP cycle time 3.2 25 ns
3 tw(ARMCLKN) Pulse width ARMCLKN high 0.45*tc(ARMCLKN) 0.55*tc(ARMCLKN) ns
2 tw(ARMCLKN) Pulse width ARMCLKN low 0.45*tc(ARMCLKN) 0.55*tc(ARMCLKN) ns
2 tw(ARMCLKP) Pulse width ARMCLKP high 0.45*tc(ARMCLKP) 0.55*tc(ARMCLKP) ns
3 tw(ARMCLKP) Pulse width ARMCLKP low 0.45*tc(ARMCLKP) 0.55*tc(ARMCLKP) ns
4 tr(ARMCLK_200 mV) Transition time ARMCLK differential rise time (200 mV) 50 350 ps
4 tf(ARMCLK_200 mV) Transition time ARMCLK differential fall time (200 mV) 50 350 ps
5 tj(ARMCLKN) Jitter, peak_to_peak _ periodic ARMCLKN 100 ps
5 tj(ARMCLKP) Jitter, peak_to_peak _ periodic ARMCLKP 100 ps
ALTCORECLK[P:N]
1 tc(ALTCORCLKN) Cycle time ALTCORECLKN cycle time 3.2 25 ns
1 tc(ALTCORECLKP) Cycle time ALTCORECLKP cycle time 3.2 25 ns
3 tw(ALTCORECLKN) Pulse width ALTCORECLKN high 0.45*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKN) ns
2 tw(ALTCORECLKN) Pulse width ALTCORECLKN low 0.45*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKN) ns
2 tw(ALTCORECLKP) Pulse width ALTCORECLKP high 0.45*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP) ns
3 tw(ALTCORECLKP) Pulse width ALTCORECLKP low 0.45*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP) ns
4 tr(ALTCORECLK_200 mV) Transition time ALTCORECLK differential rise time (200 mV) 50 350 ps
4 tf(ALTCORECLK_200 mV) Transition time ALTCORECLK differential fall time (200 mV) 50 350 ps
5 tj(ALTCORECLKN) Jitter, peak_to_peak _ periodic ALTCORECLKN 100 ps
5 tj(ALTCORECLKP) Jitter, peak_to_peak _ periodic ALTCORECLKP 100 ps
SRIOSGMIICLK[P:N]
1 tc(SRIOSGMIICLKN) Cycle time SRIOSGMIICLKN cycle time 3.2 or 6.4 or 8 ns
1 tc(SRIOSGMIICLKP) Cycle time SRIOSGMIICLKP cycle time 3.2 or 6.4 or 8 ns
3 tw(SRIOSGMIICLKN) Pulse width SRIOSGMIICLKN high 0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN) ns
2 tw(SRIOSGMIICLKN) Pulse width SRIOSGMIICLKN low 0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN) ns
2 tw(SRIOSGMIICLKP) Pulse width SRIOSGMIICLKP high 0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP) ns
3 tw(SRIOSGMIICLKP) Pulse width SRIOSGMIICLKP low 0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP) ns
4 tr(SRIOSGMIICLK_200mV) Transition time SRIOSGMIICLK differential rise time (200 mV) 50 350 ps
4 tf(SRIOSGMIICLK_200mV) Transition time SRIOSGMIICLK differential fall time (200 mV) 50 350 ps
5 tj(SRIOSGMIICLKN) Jitter, RMS SRIOSGMIICLKN 2 ps, RMS
5 tj(SRIOSGMIICLKP) Jitter, RMS SRIOSGMIICLKP 2 ps, RMS
5 tj(SRIOSGMIICLKN) Jitter, RMS SRIOSGMIICLKN (SRIO not used) 4 ps, RMS
5 tj(SRIOSGMIICLKP) Jitter, RMS SRIOSGMIICLKP (SRIO not used) 4 ps, RMS
HYPxCLK[P:N]
1 tc(HYPCLKN) Cycle time HYPCLKN cycle time 3.2 or 4 or 6.4 ns
1 tc(HYPCLKP) Cycle time HYPCLKP cycle time 3.2 or 4 or 6.4 ns
3 tw(HYPCLKN) Pulse width HYPCLKN high 0.45*tc(HYPCLKN) 0.55*tc(HYPCLKN) ns
2 tw(HYPCLKN) Pulse width HYPCLKN low 0.45*tc(HYPCLKN) 0.55*tc(HYPCLKN) ns
2 tw(HYPCLKP) Pulse width HYPCLKP high 0.45*tc(HYPCLKP) 0.55*tc(HYPCLKP) ns
3 tw(HYPCLKP) Pulse width HYPCLKP low 0.45*tc(HYPCLKP) 0.55*tc(HYPCLKP) ns
4 tr(HYPCLK) Rise time HYPCLK differential rise time (10% to 90%) 0.2*tc(HYPCLKP) ps
4 tf(HYPCLK) Fall time HYPCLK differential fall time (10% to 90%) 0.2*tc(HYPCLKP) ps
5 tj(HYPCLKN) Jitter, RMS HYPCLKN 4 ps, RMS
5 tj(HYPCLKP) Jitter, RMS HYPCLKP 4 ps, RMS
PCIECLK[P:N]
1 tc(PCIECLKN) Cycle time PCIECLKN cycle time 3.2 or 4 or 6.4 or 10 ns
1 tc(PCIECLKP) Cycle time PCIECLKP cycle time 3.2 or 4 or 6.4 or 10 ns
3 tw(PCIECLKN) Pulse width PCIECLKN high 0.45*tc(PCIECLKN) 0.55*tc(PCIECLKN) ns
2 tw(PCIECLKN) Pulse width PCIECLKN low 0.45*tc(PCIECLKN) 0.55*tc(PCIECLKN) ns
2 tw(PCIECLKP) Pulse width PCIECLKP high 0.45*tc(PCIECLKP) 0.55*tc(PCIECLKP) ns
3 tw(PCIECLKP) Pulse width PCIECLKP low 0.45*tc(PCIECLKP) 0.55*tc(PCIECLKP) ns
4 tr(PCIECLK) Rise time PCIECLK differential rise time (10% to 90%) 0.2*tc(PCIECLKP) ps
4 tf(PCIECLK) Fall time PCIECLK differential fall time (10% to 90%) 0.2*tc(PCIECLKP) ps
5 tj(PCIECLKN) Jitter, RMS PCIECLKN 4 ps, RMS
5 tj(PCIECLKP) Jitter, RMS PCIECLKP 4 ps, RMS
USBCLK[P:M]
1 tc(USBCLKN) Cycle time USBCLKM cycle time 5 50 ns
1 tc(USBCLKP) Cycle time USBCLKP cycle time 5 50 ns
3 tw(USBCLKN) Pulse width USBCLKM high 0.45*tc(USBCLKN) 0.55*tc(USBCLKN) ns
2 tw(USBCLKN) Pulse width USBCLKM low 0.45*tc(USBCLKN) 0.55*tc(USBCLKN) ns
2 tw(USBCLKP) Pulse width USBCLKP high 0.45*tc(USBCLKP) 0.55*tc(USBCLKP) ns
3 tw(USBCLKP) Pulse width USBCLKP low 0.45*tc(USBCLKP) 0.55*tc(USBCLKP) ns
4 tr(USBCLK) Rise time USBCLK differential rise time (10% to 90%) TBD ps
4 tf(USBCLK) Fall time USBCLK differential fall time (10% to 90%) TBD ps
5 tj(USBCLKN) Jitter, RMS USBCLKM 3 ps, RMS
5 tj(USBCLKP) Jitter, RMS USBCLKP 3 ps, RMS
See Hardware Design Guide for KeyStone II Devices for detailed recommendations.
66AK2H14 66AK2H12 66AK2H06 PLL1_Timing_NySh.gif Figure 11-21 Main PLL Controller, SRIO, HyperLink, PCIe, USB Clock Input Timing
66AK2H14 66AK2H12 66AK2H06 Clock_Transition_Time_KS_1-KS_2_LJCB.gif Figure 11-22 Main PLL Transition Time
66AK2H14 66AK2H12 66AK2H06 Clock_Rise_and_Fall_Time_Snowbush.gif Figure 11-23 HYP0CLK, HYP1CLK, and PCIECLK Rise and Fall Times
66AK2H14 66AK2H12 66AK2H06 Clock_Rise_and_Fall_Time_Synopsys.gif Figure 11-24 USBCLK Rise and Fall Times

DDR3A PLL and DDR3B PLL

The DDR3A PLL and DDR3B PLL generate interface clocks for the DDR3A and DDR3B memory controllers. When coming out of power-on reset, DDR3A PLL and DDR3B PLL are programmed to a valid frequency during the boot configuration process before being enabled and used.

DDR3A PLL and DDR3B PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See Hardware Design Guide for KeyStone II Devices for detailed recommendations.

Figure 11-25 shows a block diagram of the DDR3A PLL and DDR3B PLL.

66AK2H14 66AK2H12 66AK2H06 DDR3_PLL_Block_Diagram_661x.gif Figure 11-25 DDR3A PLL and DDR3B PLL Block Diagram

DDR3A PLL and DDR3B PLL Control Registers

The DDR3A PLL and DDR3B PLL, which are used to drive the DDR3A PHY and DDR3B PHY for the EMIF, do not use a PLL controller. DDR3A PLL and DDR3B PLL can be controlled using the DDR3APLLCTL0/DDR3BPLLCTL0 and DDR3APLLCTL1/DDR3BPLLCTL1 registers in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configurable values, see Section 10.1.4. See Section 10.2.3.4 for the address location of the registers and locking and unlocking sequences for accessing the registers. These registers are reset on POR only.

The DDR3A PLL and DDR3B PLL control registers are shown in Figure 11-26 and Figure 11-27 and described in Table 11-30 and Table 11-31.

Figure 11-26 DDR3A PLL and DDR3B PLL Control Register 0 (DDR3APLLCTL0/DDR3BPLLCTL0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWADJ[7:0] BYPASS CLKOD PLLM PLLD
RW-0000 1001 RW-1 RW-0001 RW-0000000010011 RW-000000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions

Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.
23 BYPASS PLL bypass mode:
  • 0 = PLL is not in BYPASS mode
  • 1 = PLL is in BYPASS mode
22-19 CLKOD A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1
18-6 PLLM A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply factor minus 1
5-0 PLLD A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide value minus 1
Figure 11-27 DDR3A PLL and DDR3B PLL Control Register 1 (DDR3APLLCTL0/DDR3BPLLCTL1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PLLRST Reserved ENSAT Reserved BWADJ[11:8]
RW-00000000000000000 RW-0 RW-0000000 RW-0 R-00 RW-0000
Legend: RW = Read/Write; – n = value after reset

Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions

Bit Field Description
31-15 Reserved Reserved
14 PLLRST PLL Reset bit
  • 0 = PLL Reset is released
  • 1 = PLL Reset is asserted
13-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper PLL operation
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.

DDR3A PLL and DDR3B PLL Device-Specific Information

As shown in Figure 11-25, the output of DDR3A PLL and DDR3B PLL (PLLOUT) is divided by 2 and directly fed to the DDR3A and DDR3B memory controller. During power-on resets, the internal clocks of the DDR3 PLL are affected as described in Section 11.4. The DDR3 PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

DDR3 PLL Input Clock Electrical Data and Timing

Table 11-32 applies to both DDR3A and DDR3B memory interfaces.

Table 11-32 DDR3 PLL DDRCLK(N|P) Timing Requirements

(see Figure 11-28 and Figure 11-22)
NO. MIN MAX UNIT
DDRCLK[P:N]
1 tc(DDRCLKN) Cycle time _ DDRCLKN cycle time 3.2 25 ns
1 tc(DDRCLKP) Cycle time _ DDRCLKP cycle time 3.2 25 ns
3 tw(DDRCLKN) Pulse width _ DDRCLKN high 0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
2 tw(DDRCLKN) Pulse width _ DDRCLKN low 0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
2 tw(DDRCLKP) Pulse width _ DDRCLKP high 0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
3 tw(DDRCLKP) Pulse width _ DDRCLKP low 0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
4 tr(DDRCLK_200 mV) Transition time _ DDRCLK differential rise time (200 mV) 50 350 ps
4 tf(DDRCLK_200 mV) Transition time _ DDRCLK differential fall time (200 mV) 50 350 ps
5 tj(DDRCLKN) Jitter, peak_to_peak _ periodic DDRCLKN 0.02*tc(DDRCLKN) ps
5 tj(DDRCLKP) Jitter, peak_to_peak _ periodic DDRCLKP 0.02*tc(DDRCLKP) ps
66AK2H14 66AK2H12 66AK2H06 DDR3_PLL_DDRCLK_Timing_NySh.gif Figure 11-28 DDR3 PLL DDRCLK Timing

PASS PLL

The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select the input source of the PASS PLL as either the output of the Main PLL mux or the PASSCLK clock reference source. When coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be programmed to a valid frequency before being enabled and used.

PASS PLL power is supplied via the PASS PLL power-supply pin (AVDDA3). An external EMI filter circuit must be added to all PLL supplies. See Hardware Design Guide for KeyStone II Devices for detailed recommendations.

The PASS PLL block diagram is shown in Figure 11-29.

66AK2H14 66AK2H12 66AK2H06 PASS_PLL_Block_Diagram_661x.gif Figure 11-29 PASS PLL Block Diagram

PASS PLL Local Clock Dividers

The clock signal from the PASS PLL controller is routed to the network coprocessor. The NetCP module has two internal dividers with fixed division ratios, as shown in .

PASS PLL Control Registers

The PASS PLL, which is used to drive the network coprocessor, does not use a PLL controller. PASS PLL can be controlled using the PAPLLCTL0 and PAPLLCTL1 registers in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configuration values, see Section 10.1.4. See Section 10.2.3.4 for the address location of the registers and locking and unlocking sequences for accessing these registers. These registers are reset on POR only.

The PASS PLL control registers are shown in Figure 11-30 and Figure 11-31 and described in Table 11-33 and Table 11-34.

Figure 11-30 PASS PLL Control Register 0 (PASSPLLCTL0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWADJ[7:0] BYPASS CLKOD PLLM PLLD
RW-0000 1001 RW-1 RW-0001 RW-0000000010011 RW-000000
LEGEND: RW = Read/Write; -n = value after reset

Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)

Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.
23 BYPASS PLL bypass mode:
  • 0 = PLL is not in BYPASS mode
  • 1 = PLL is in BYPASS mode
22-19 CLKOD A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1
18-6 PLLM A 13-bit field that selects the values for the multiplication factor (see note below). PLLM field is loaded with the multiply factor minus 1.
5-0 PLLD A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
Figure 11-31 PASS PLL Control Register 1 (PASSPLLCTL1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PLLRST PAPLL Reserved ENSAT Reserved BWADJ[11:8]
RW-00000000000000000 RW-0 RW-0 RW-0000000 RW-0 R-00 RW-0000
Legend: RW = Read/Write; – n = value after reset

Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)

Bit Field Description
31-15 Reserved Reserved
14 PLLRST PLL Reset bit
  • 0 = PLL Reset is released
  • 1 = PLL Reset is asserted
13 PAPLL
  • 0 = Not supported
  • 1 = PAPLL
12-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper PLL operation
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1.

PASS PLL Device-Specific Information

As shown in Figure 11-29, the output of PASS PLL (PLLOUT) is divided by 3 and directly fed to the Network Coprocessor. During power-on resets, the internal clocks of the PASS PLL are affected as described in Section 11.4. The PASS PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any other resets.

PASS PLL Input Clock Electrical Data and Timing

Table 11-35 shows the PASS PLL timing requirements.

Table 11-35 PASS PLL Timing Requirements

(see Figure 11-32 and Figure 11-22)
NO. MIN MAX UNIT
PASSCLK[P:N]
1 tc(PASSCLKN) Cycle time _ PASSCLKN cycle time 3.2 6.4 ns
1 tc(PASSCLKP) Cycle time _ PASSCLKP cycle time 3.2 6.4 ns
3 tw(PASSCLKN) Pulse width _ PASSCLKN high 0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN) ns
2 tw(PASSCLKN) Pulse width _ PASSCLKN low 0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN) ns
2 tw(PASSCLKP) Pulse width _ PASSCLKP high 0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP) ns
3 tw(PASSCLKP) Pulse width _ PASSCLKP low 0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP) ns
4 tr(PASSCLK_200mV) Transition time _ PASSCLK differential rise time (200 mV) 50 350 ps
4 tf(PASSCLK_200mV) Transition time _ PASSCLK differential fall time (200 mV) 50 350 ps
5 tj(PASSCLKN) Jitter, peak_to_peak _ periodic PASSCLKN 100 ps, pk-pk
5 tj(PASSCLKP) Jitter, peak_to_peak _ periodic PASSCLKP 100 ps, pk-pk
66AK2H14 66AK2H12 66AK2H06 PASS_PLL_Timing.gif Figure 11-32 PASS PLL Timing

External Interrupts

External Interrupts Electrical Data and Timing

Table 11-36 shows the NMI and LRESET timing requirements.

Table 11-36 NMI and LRESET Timing Requirements(1)

(see Figure 11-33)
NO. MIN MAX UNIT
1 tsu( LRESETLRESETNMIEN) Setup time – LRESET valid before LRESETNMIEN low 12*P ns
1 tsu( NMILRESETNMIEN) Setup time – NMI valid before LRESETNMIEN low 12*P ns
1 tsu(CORESELn – LRESETNMIEN) Setup time – CORESEL[3:0] valid before LRESETNMIEN low 12*P ns
2 th(LRESETNMIENLRESET) Hold time – LRESET valid after LRESETNMIEN high 12*P ns
2 th(LRESETNMIENNMI) Hold time – NMI valid after LRESETNMIEN high 12*P ns
2 th(LRESETNMIEN – CORESELn) Hold time – CORESEL[3:0] valid after LRESETNMIEN high 12*P ns
3 tw(LRESETNMIEN) Pulsewidth – LRESETNMIEN low width 12*P ns
P = 1/SYSCLK1 clock frequency in ns.
66AK2H14 66AK2H12 66AK2H06 NMI_and_Reset_Timing_NySh.gif Figure 11-33 NMI and LRESET Timing

DDR3A and DDR3B Memory Controllers

The 72-bit DDR3 memory controller bus of the 66AK2Hxx is used to interface to JEDEC standard-compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and does not share the bus with any other type of peripheral.

DDR3 Memory Controller Device-Specific Information

The 66AK2Hxx includes one 64-bit wide, 1.35-V / 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.

Due to the complicated nature of the interface, a limited number of topologies are supported to provide a 16-bit, 32-bit, or 64-bit interface.

The DDR3 electrical requirements are fully specified in the DDR JEDEC specification JESD79-3C. Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank topologies to be supported by the interface:

  • 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
  • 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
  • 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
  • 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)
  • 64-bit: Four 16-bit SDRAMs
  • 64-bit: Eight 8-bit SDRAMs
  • 32-bit: Two 16-bit SDRAMs
  • 32-bit: Four 8-bit SDRAMs
  • 16-bit: One 16-bit SDRAM
  • 16-bit: Two 8-bit SDRAMs

The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible DDR3 devices and provide the printed-circuit board (PCB) solution and guidelines directly to the user.

A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes before signaling to master B that the message is ready, when master B attempts to read the software message, the master B read may bypass the master A write. Thus, master B may read stale data and receive an incorrect message.

Some master peripherals (for example, EDMA3 transfer controllers with TCCMOD=0) always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering in the software.

If master A does not wait for an indication that a write is complete, it must perform the following workaround:

  1. Perform the required write to DDR3 memory space.
  2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
  3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
  4. Indicate to master B that the data is ready to be read after completion of the read in Step 3. The completion of the read in Step 3 ensures that the previous write was done.

DDR3 Slew Rate Control

The DDR3 slew rate is controlled by use of the PHY registers. See the Keystone II Architecture DDR3 Memory Controller User's Guide for details.

DDR3 Memory Controller Electrical Data and Timing

DDR3 Design Requirements for KeyStone Devices specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the DDR3 JEDEC Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met. Therefore, no electrical data and timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

I2C Peripheral

The Inter-Integrated Circuit (I2C) module provides an interface between SoC and other devices compliant with Philips Semiconductors (now NXP Semiconductors) Inter-Integrated Circuit bus specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the device through the I2C module.

I2C Device-Specific Information

The device includes multiple I2C peripheral modules.

NOTE

When using the I2C module, ensure there are external pullup resistors on the SDA and SCL pins.

The I2C modules on the 66AK2Hxx may be used by the SoC to control local peripheral ICs (DACs, ADCs, and so forth), communicate with other controllers in a system, or to implement a user interface.

The I2C port supports:

  • Compatibility with Philips I2C specification revision 2.1 (January 2000)
  • Fast mode up to 400 kbps (no fail-safe I/O buffers)
  • Noise filter to remove noise of 50 ns or less
  • 7-bit and 10-bit device addressing modes
  • Multimaster (transmit/receive) and slave (transmit/receive) functionality
  • Events: DMA, interrupt, or polling
  • Slew-rate limited open-drain output buffers

Figure 11-34 shows a block diagram of the I2C module.

66AK2H14 66AK2H12 66AK2H06 I2C_Module_Block_Diagram_NySh.gif Figure 11-34 I2C Module Block Diagram

I2C Peripheral Register Description

Table 11-37 lists the I2C registers.

Table 11-37 I2C Registers

HEX ADDRESS OFFSETS ACRONYM REGISTER NAME
0x0000 ICOAR I2C Own Address Register
0x0004 ICIMR I2C Interrupt Mask/status Register
0x0008 ICSTR I2C Interrupt Status Register
0x000C ICCLKL I2C Clock Low-time Divider Register
0x0010 ICCLKH I2C Clock High-time Divider Register
0x0014 ICCNT I2C Data Count Register
0x0018 ICDRR I2C Data Receive Register
0x001C ICSAR I2C Slave Address Register
0x0020 ICDXR I2C Data Transmit Register
0x0024 ICMDR I2C Mode Register
0x0028 ICIVR I2C Interrupt Vector Register
0x002C ICEMDR I2C Extended Mode Register
0x0030 ICPSC I2C Prescaler Register
0x0034 ICPID1 I2C Peripheral Identification Register 1 [value: 0x0000 0105]
0x0038 ICPID2 I2C Peripheral Identification Register 2 [value: 0x0000 0005]
0x003C -0x007F - Reserved

I2C Electrical Data and Timing

Table 11-38 shows the I2C timing requirements and Table 11-39 shows the I2C switching characteristics.

Table 11-38 I2C Timing Requirements(1)

(see Figure 11-35)
NO. STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 µs
2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs
3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(2) ns
7 th(SCLL-SDAV) Hold time, SDA valid after SCL low (for I2C bus devices) 0(3) 3.45 0(3) 0.9(4) µs
8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(5) 300 ns
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(5) 300 ns
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(5) 300 ns
12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb(5) 300 ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
Cb (5) Capacitive load for each bus line 400 400 pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has to be met only if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
66AK2H14 66AK2H12 66AK2H06 I2C_Receive_Timings_NySh.gif Figure 11-35 I2C Receive Timings

Table 11-39 I2C Switching Characteristics(1)

(see Figure 11-36)
NO. PARAMETER STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 µs
17 tsu(SCLH-SDAL) Setup time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 µs
18 th(SDAL-SCLL) Hold time, SDA low after SCL low (for a START and a repeated START condition) 4 0.6 µs
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
21 td(SDAV-SDLH) Delay time, SDA valid to SCL high 250 100 ns
22 tv(SDLL-SDAV) Valid time, SDA valid after SCL low (for I2C bus devices) 0 0 0.9 µs
23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(1) 300 ns
25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(1) 300 ns
26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(1) 300 ns
27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb(1) 300 ns
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs
Cp Capacitance for each I2C pin 10 10 pF
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
66AK2H14 66AK2H12 66AK2H06 I2C_Transmit_Timings_NySh.gif Figure 11-36 I2C Transmit Timings

SPI Peripheral

The Serial Peripheral Interconnect (SPI) module provides an interface between the SoC and other SPI-compliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot. The SPI module on 66AK2Hxx is supported only in master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander.

SPI Electrical Data and Timing

Table 11-40 shows the SPI timing requirements and Table 11-41 shows the SPI switching characteristics.

Table 11-40 SPI Timing Requirements

(see Figure 11-37)
NO. MIN MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0 2 ns
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1 2 ns
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0 2 ns
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1 2 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0 5 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1 5 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0 5 ns
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1 5 ns

Table 11-41 SPI Switching Characteristics

(see Figure 11-37 and Figure 11-38)
NO. PARAMETER MIN MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1 tc(SPC) Cycle time, SPICLK, all master modes 3*P2(1) ns
2 tw(SPCH) Pulse width high, SPICLK, all master modes 0.5*(3*P2) – 1 ns
3 tw(SPCL) Pulse width low, SPICLK, all master modes 0.5*(3*P2) – 1 ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK. Polarity = 0, Phase = 0. 5 ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK. Polarity = 0, Phase = 1. 5 ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK Polarity = 1, Phase = 0 5 ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK Polarity = 1, Phase = 1 5 ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK. Polarity = 0 Phase = 0 2 ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 0 Phase = 1 2 ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 1 Phase = 0 2 ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 1 Phase = 1 2 ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 0 0.5*tc – 2 ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 1 0.5*tc – 2 ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 0 0.5*tc – 2 ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 1 0.5*tc – 2 ns
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 0 Phase = 0 2*P2 – 5 2*P2 + 5 ns
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 0 Phase = 1 0.5*tc + (2*P2) – 5 0.5*tc + (2*P2) + 5 ns
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 1 Phase = 0 2*P2 – 5 2*P2 + 5 ns
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 1 Phase = 1 0.5*tc + (2*P2) – 5 0.5*tc + (2*P2) + 5 ns
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 0 Phase = 0 1*P2 – 5 1*P2 + 5 ns
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 0 Phase = 1 0.5*tc + (1*P2) – 5 0.5*tc + (1*P2) + 5 ns
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 1 Phase = 0 1*P2 – 5 1*P2 + 5 ns
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 1 Phase = 1 0.5*tc + (1*P2) – 5 0.5*tc + (1*P2) + 5 ns
tw(SCSH) Minimum inactive time on SPISCSx\ pin between two transfers when SPISCSx\ is not held using the CSHOLD feature. 2*P2 – 5 ns
P2=1/(SYSCLK1/6)
66AK2H14 66AK2H12 66AK2H06 SPI_Master_Mode_Timing_Diagrams_-_Base_Timings_for_3_Pin_Modes_NySh.gif Figure 11-37 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
66AK2H14 66AK2H12 66AK2H06 SPI_Additional_Timings_for_4_Pin_Master_Mode_with_Chip_Select_NySh.gif Figure 11-38 SPI Additional Timings for 4-Pin Master Mode with Chip Select Option

HyperLink Peripheral

The 66AK2Hxx includes HyperLinks for companion device interfaces. This is a four-lane SerDes interface designed to operate at up to 10 Gbps per lane from pin-to-pin. The interface is used to connect with external accelerators that are manufactured using TI libraries. The HyperLink lines must be connected with DC coupling.

The interface includes the serial station management interfaces used to send power management and flow messages between devices. Each HyperLink interface consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire input buses and two 2-wire output buses. Each 2-wire bus includes a data signal and a clock signal.

Table 11-42 shows the Hyperlink timing requirements and Table 11-43 shows the Hyperlink switching characteristics.

Table 11-42 HyperLink Peripheral Timing Requirements

(see Figure 11-39, Figure 11-40, and Figure 11-41)
NO. MIN MAX UNIT
FL Interface
1 tc(HYPTXFLCLK) Clock period – HYPTXFLCLK (C1) 5.75 ns
2 tw(HYPTXFLCLKH) High pulse width – HYPTXFLCLK 0.4*C1 0.6*C1 ns
3 tw(HYPTXFLCLKL) Low pulse width – HYPTXFLCLK 0.4*C1 0.6*C1 ns
6 tsu(HYPTXFLDAT-HYPTXFLCLKH) Setup time – HYPTXFLDAT valid before HYPTXFLCLK high 1 ns
7 th(HYPTXFLCLKH-HYPTXFLDAT) Hold time – HYPTXFLDAT valid after HYPTXFLCLK high 1 ns
6 tsu(HYPTXFLDAT-HYPTXFLCLKL) Setup time – HYPTXFLDAT valid before HYPTXFLCLK low 1 ns
7 th(HYPTXFLCLKL-HYPTXFLDAT) Hold time – HYPTXFLDAT valid after HYPTXFLCLK low 1 ns
PM Interface
1 tc(HYPRXPMCLK) Clock period – HYPRXPMCLK (C3) 5.75 ns
2 tw(HYPRXPMCLK) High pulse width – HYPRXPMCLK 0.4*C3 0.6*C3 ns
3 tw(HYPRXPMCLK) Low pulse width – HYPRXPMCLK 0.4*C3 0.6*C3 ns
6 tsu(HYPRXPMDAT-HYPRXPMCLKH) Setup time – HYPRXPMDAT valid before HYPRXPMCLK high 1 ns
7 th(HYPRXPMCLKH-HYPRXPMDAT) Hold time – HYPRXPMDAT valid after HYPRXPMCLK high 1 ns
6 tsu(HYPRXPMDAT-HYPRXPMCLKL) Setup time – HYPRXPMDAT valid before HYPRXPMCLK low 1 ns
7 th(HYPRXPMCLKL-HYPRXPMDAT) Hold time – HYPRXPMDAT valid after HYPRXPMCLK low 1 ns

Table 11-43 HyperLink Peripheral Switching Characteristics

(see Figure 11-39, Figure 11-40, and Figure 11-41)
NO. PARAMETER MIN MAX UNIT
FL Interface
1 tc(HYPRXFLCLK) Clock period – HYPRXFLCLK (C2) 6.4 ns
2 tw(HYPRXFLCLKH) High pulse width – HYPRXFLCLK 0.4*C2 0.6*C2 ns
3 tw(HYPRXFLCLKL) Low pulse width – HYPRXFLCLK 0.4*C2 0.6*C2 ns
4 tosu(HYPRXFLDAT-HYPRXFLCLKH) Setup time – HYPRXFLDAT valid before HYPRXFLCLK high 0.25*C2-0.4 ns
5 toh(HYPRXFLCLKH-HYPRXFLDAT) Hold time – HYPRXFLDAT valid after HYPRXFLCLK high 0.25*C2-0.4 ns
4 tosu(HYPRXFLDAT-HYPRXFLCLKL) Setup time – HYPRXFLDAT valid before HYPRXFLCLK low 0.25*C2-0.4 ns
5 toh(HYPRXFLCLKL-HYPRXFLDAT) Hold time – HYPRXFLDAT valid after HYPRXFLCLK low 0.25*C2-0.4 ns
PM Interface
1 tc(HYPTXPMCLK) Clock period – HYPTXPMCLK (C4) 6.4 ns
2 tw(HYPTXPMCLK) High pulse width – HYPTXPMCLK 0.4*C4 0.6*C4 ns
3 tw(HYPTXPMCLK) Low pulse width – HYPTXPMCLK 0.4*C4 0.6*C4 ns
4 tosu(HYPTXPMDAT-HYPTXPMCLKH) Setup time – HYPTXPMDAT valid before HYPTXPMCLK high 0.25*C2-0.4 ns
5 toh(HYPTXPMCLKH-HYPTXPMDAT) Hold time – HYPTXPMDAT valid after HYPTXPMCLK high 0.25*C2-0.4 ns
4 tosu(HYPTXPMDAT-HYPTXPMCLKL) Setup time – HYPTXPMDAT valid before HYPTXPMCLK low 0.25*C2-0.4 ns
5 toh(HYPTXPMCLKL-HYPTXPMDAT) Hold time – HYPTXPMDAT valid after HYPTXPMCLK low 0.25*C2-0.4 ns
66AK2H14 66AK2H12 66AK2H06 HyperLink_Station_Mgmt_Clock_Timing_K2.gif Figure 11-39 HyperLink Station Management Clock Timing
66AK2H14 66AK2H12 66AK2H06 HyperLink_Station_Mgmt_Trans_Timing_K2.gif
<xx> represents the interface that is being used: PM or FL
Figure 11-40 HyperLink Station Management Transmit Timing
66AK2H14 66AK2H12 66AK2H06 HyperLink_Station_Mgmt_Rec_Timing_K2.gif
<xx> represents the interface that is being used: PM or FL
Figure 11-41 HyperLink Station Management Receive Timing

UART Peripheral

The universal asynchronous receiver/transmitter (UART) module provides an interface between the device and a UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550 asynchronous communications element which, in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the SoC of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the C66x CorePac to be sent to the peripheral device. The C66x CorePac can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on UART, see the KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User's Guide.

Table 11-44 shows the UART timing requirements and Table 11-45 shows the UART switching characteristics.

Table 11-44 UART Timing Requirements

(see Figure 11-42 and Figure 11-43)
NO. MIN MAX UNIT
Receive Timing
4 tw(RXSTART) Pulse width, receive start bit 0.96U(1) 1.05U ns
5 tw(RXH) Pulse width, receive data/parity bit high 0.96U 1.05U ns
5 tw(RXL) Pulse width, receive data/parity bit low 0.96U 1.05U ns
6 tw(RXSTOP1) Pulse width, receive stop bit 1 0.96U 1.05U ns
6 tw(RXSTOP15) Pulse width, receive stop bit 1.5 0.96U 1.05U ns
6 tw(RXSTOP2) Pulse width, receive stop bit 2 0.96U 1.05U ns
Autoflow Timing Requirements
8 td(CTSL-TX) Delay time, CTS asserted to START bit transmit P(2) 5P ns
U = UART baud time = 1/programmed baud rate
P = 1/(SYSCLK1/6)
66AK2H14 66AK2H12 66AK2H06 UART_Receive_Timing_Waveform_NySh.gif Figure 11-42 UART Receive Timing Waveform
66AK2H14 66AK2H12 66AK2H06 UART_CTS_Autoflow_Timing_Waveform_NySh.gif Figure 11-43 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform

Table 11-45 UART Switching Characteristics

(see Figure 11-44 and Figure 11-45)
NO. PARAMETER MIN MAX UNIT
Transmit Timing
1 tw(TXSTART) Pulse width, transmit start bit U(1)- 2 U + 2 ns
2 tw(TXH) Pulse width, transmit data/parity bit high U – 2 U + 2 ns
2 tw(TXL) Pulse width, transmit data/parity bit low U – 2 U + 2 ns
3 tw(TXSTOP1) Pulse width, transmit stop bit 1 U – 2 U + 2 ns
3 tw(TXSTOP15) Pulse width, transmit stop bit 1.5 1.5 × (U – 2) 1.5 × ('U + 2) ns
3 tw(TXSTOP2) Pulse width, transmit stop bit 2 2 × (U – 2) 2 × ('U + 2) ns
Autoflow Timing Requirements
7 td(RX-RTSH) Delay time, STOP bit received to RTS deasserted P(2) 5P ns
U = UART baud time = 1/programmed baud rate
P = 1/(SYSCLK1/6)
66AK2H14 66AK2H12 66AK2H06 UART_Transmit_Timing_Waveform_NySh.gif Figure 11-44 UART Transmit Timing Waveform
66AK2H14 66AK2H12 66AK2H06 UART_RTS_Autoflow_Timing_Waveform_NySh.gif Figure 11-45 UART RTS (Request-to-Send Output) – Autoflow Timing Waveform

PCIe Peripheral

The two-lane PCI express (PCIe) module on 66AK2Hxx provides an interface between the device and other PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed data transfer at rates up to 5.0 Gbps per lane on the serial links. For more information, see the KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User's Guide.

Packet Accelerator

The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as UDP ports. It maintains 8k multiple-in, multiple-out hardware queues and also provides checksum capability as well as some QoS capabilities. The PA enables a single IP address to be used for a multicore device and can process up to 1.5 Mpps. The Packet Accelerator is coupled with the Network Coprocessor. For more information, see the KeyStone Architecture Packet Accelerator (PA) User’s Guide.

Security Accelerator

The Security Accelerator (SA) provides wire-speed processing on 1 Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air interface security protocols. It functions on the packet level with the packet and the associated security context being one of the above three types. The Security Accelerator is coupled with the Network Coprocessor, and receives the packet descriptor containing the security context in the buffer descriptor and the data to be encrypted/decrypted in the linked buffer descriptor. For more information, see the KeyStone Architecture Security Accelerator (SA) User’s Guide .

Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem

The gigabit Ethernet (GbE) switch subsystem provides an efficient interface between the device and the networked community. The Ethernet Media Access Controller (EMAC) supports 10Base-T (10 Mbits/second), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with the Network Coprocessor. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide.

An address range is assigned to the 66AK2Hxx. Each individual device has a 48-bit MAC address and consumes only one unique MAC address out of the range. There are two registers to hold these values, MACID1[31:0] (32 bits) and MACID2[15:0] (16 bits). The MACID1 and MACID2 registers are shown in Figure 11-46 and Figure 11-47 and described in Table 11-46 and Table 11-47.

Figure 11-46 MACID1 Register (MMR Address 0x02620110)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACID
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate

Table 11-46 MACID1 Register Field Descriptions

Bit Field Description
31-0 MAC ID MAC ID. Lower 32 bits.
Figure 11-47 MACID2 Register (MMR Address 0x02620114)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC Reserved FLOW BCAST MACID
R+,cccc cccc R,+rr rrrr R,+z R,+y R,+xxxx xxxx xxxx xxxx
LEGEND: R = Read only; -x = value is indeterminate

Table 11-47 MACID2 Register Field Descriptions

Bit Field Description
31-24 CRC Variable
23-18 Reserved 000000
17 FLOW MAC Flow Control
  • 0 = Off
  • 1 = On
16 BCAST Default m/b-cast reception
  • 0 = Broadcast
  • 1 = Disabled
15-0 MAC ID MAC ID. Upper 16 bits.

There is a central processor time synchronization (CPTS) submodule in the Ethernet switch module that can be used for time synchronization. Programming this register selects the clock source for the CPTS_RCLK. See the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide for the register address and other details about the time synchronization submodule. The register CPTS_RFTCLK_SEL for reference clock selection of the time synchronization submodule is shown in Figure 11-48 and described in Table 11-48.

Figure 11-48 RFTCLK Select Register (CPTS_RFTCLK_SEL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CPTS_RFTCLK_SEL
R-0 RW-0
Legend: R = Read only; -x, value is indeterminate

Table 11-48 RFTCLK Select Register Field Descriptions

Bit Field Description
31-4 Reserved Reserved. Read as 0.
3-0 CPTS_RFTCLK_SEL Reference clock select. This signal is used to control an external multiplexer that selects one of 8 clocks for time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the TS_CTL register.
  • 0000 = SYSCLK2
  • 0001 = SYSCLK3
  • 0010 = TIMI0
  • 0011 = TIMI1
  • 1000 = TSREFCLK
  • Others = Reserved

SGMII and XFI Management Data Input/Output (MDIO)

The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the gigabit Ethernet (GbE) and 10-gigabit Ethernet (10GbE) switch subsystems for correct operation. The module allows almost transparent operation of the MDIO interface, with very little attention from the SoC. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide and the KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide.

The MDIO timing requirements are shown in Table 11-49 and the MDIO switching characteristics are shown in Table 11-50.

Table 11-49 MDIO Timing Requirements

(see Figure 11-49)
NO. MIN MAX UNIT
1 tc(MDCLK) Cycle time, MDCLK 400 ns
2 tw(MDCLKH) Pulse duration, MDCLK high 180 ns
3 tw(MDCLKL) Pulse duration, MDCLK low 180 ns
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 10 ns
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 10 ns
tt(MDCLK) Transition time, MDCLK 5 ns
66AK2H14 66AK2H12 66AK2H06 MDIO_Input_Timing_KS2.gif Figure 11-49 MDIO Input Timing

Table 11-50 MDIO Switching Characteristics

(see Figure 11-50)
NO. PARAMETER MIN MAX UNIT
6 td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO data output valid 10 300 ns
7 th(MDCLKH-MDIO) Hold time, MDIO data output valid after MDCLK high 10 ns
8 td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO Hi-Z 10 300 ns
66AK2H14 66AK2H12 66AK2H06 MDIO_Output_Timing_KS2.gif Figure 11-50 MDIO Output Timing

Ten-Gigabit Ethernet (10GbE) Switch Subsystem

The 3-port Ten Gigabit Ethernet Switch Subsystem (different from the Network Coprocessor integrated switch) includes a stand-alone EMAC switch subsystem and a 2-lane SerDes macro. The 2-lane macro enables only 2 external ports. It does not include any packet acceleration or security acceleration engine.

10GbE Supported Features

The key features of the 10GbE module are listed below:

  • 10 Gbps EMAC switch subsystem
    • MDIO: Media-dependent input/output module
    • SGMII Interface for 10/100/1000 and 10GBASE-KR for 10G
    • Ethernet switch with wire-rate switching (only two external ports are supported by the SerDes)
    • CPTS module that supports time-stamping for IEEE 1588v2 with support for eight hardware push events and generation of compare output pulses
    • Supports XFI electrical interface
  • CPDMA

The CPDMA component provides CPPI 4.2 compatible functionality, and provides a 128-bit-wide data path to the TeraNet, enabling:

  • Support for 8 transmit channel and 16 receive channels
  • Support for reset isolation option

For more information, see the KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide.

Timers

The timers can be used to time events, count events, generate pulses, interrupt the CorePacs, and send synchronization events to the EDMA3 channel controller.

Timers Device-Specific Information

The 66AK2Hxx device has up to twenty 64-bit timers in total, (66AK2H12 has 20 timers and the 66AK2H06 has 14) of which Timer0 through Timer3 (66AK2H06) or Timer7 (66AK2H12) are dedicated to each of the up to eight C66x CorePacs as watchdog timers and can also be used as general-purpose timers. Timer16 and Timer17 (66AK2H06) or (66AK2H12).Timer16 through Timer19 are dedicated to each of the Cortex-A15 processor cores as a watchdog timer and can also be used as general-purpose timers. The remaining timers can be configured as general-purpose timers only, with each timer programmed as a 64-bit timer or as two separate 32-bit timers.

When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses (rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable period. When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter. The module clock for each timer module is SYSCLK1, with a shared local divider (not programmable) of /6 (timer module clock frequency = SYSCLK1/6). Refer to Table 11-13.

When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again. If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming the Reset Type Status register (RSTYPE) (see Section 11.5.2.6) and the type of reset initiated can set by programming the Reset Configuration register (RSTCFG) (see Section 11.5.2.8). For more information, see the KeyStone Architecture Timer 64P User's Guide.

Timers Electrical Data and Timing

Table 11-51 and Table 11-52 list timing requirements and switching characteristics of the timers.

Table 11-51 Timer Input Timing Requirements(1)

(see Figure 11-51)
NO. MIN MAX UNIT
1 tw(TINPH) Pulse duration, high 12C ns
2 tw(TINPL) Pulse duration, low 12C ns
C = 1/SYSCLK1 clock frequency in ns

Table 11-52 Timer Output Switching Characteristics(1)

(see Figure 11-51)
NO. PARAMETER MIN MAX UNIT
3 tw(TOUTH) Pulse duration, high 12C – 3 ns
4 tw(TOUTL) Pulse duration, low 12C – 3 ns
C = 1/SYSCLK1 clock frequency in ns.
66AK2H14 66AK2H12 66AK2H06 Timer_Timing_NySh.gif Figure 11-51 Timer Timing

Serial RapidIO (SRIO) Port

The SRIO port on the device is a high-performance, low pin-count SerDes interconnect. SRIO interconnects in a baseband board design provide connectivity and control among the components. The device supports four 1× Serial RapidIO links or one 4× Serial RapidIO link. The SRIO interface is designed to operate at a data rate of up to 5 Gbps per differential pair. This equals 20 raw GBaud/s for the 4× SRIO port, or approximately 15 Gbps data throughput rate.

The PHY part of the SRIO consists of the physical layer and includes the input and output buffers (each serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the parallel-to-serial/serial-to-parallel converters.

For more information, see the KeyStone Architecture Serial RapidIO (SRIO) User's Guide.

Serial RapidIO Device-Specific Information

The approach to specifying interface timing for the SRIO Port is different from other interfaces. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models.

The Serial RapidIO peripheral is a master peripheral in the device. It conforms to the RapidIO™ Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.

For the SRIO port, Texas Instruments provides a PCB solution showing two TI SRIO-enabled DSPs connected together via a 4× SRIO link. TI has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met.

NOTE

TI supports only designs that follow the board design guidelines outlined in the RapidIO™ Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.

General-Purpose Input/Output (GPIO)

GPIO Device-Specific Information

The GPIO peripheral pins are used for general-purpose input/output for the device. These pins are also used to configure the device at boot time.

For more detailed information on device/ and peripheral configuration and the 66AK2Hxx device pin multiplexing, see Section 10.2.

These GPIO pins can also be used to generate individual core interrupts (no support of bank interrupt) and EDMA events.

GPIO Peripheral Register Description

Table 11-53 lists the GPIO registers.

Table 11-53 GPIO Registers

HEX ADDRESS OFFSETS ACRONYM REGISTER NAME
0x0008 BINTEN GPIO interrupt per bank enable register
0x000C - Reserved
0x0010 DIR GPIO Direction Register
0x0014 OUT_DATA GPIO Output Data Register
0x0018 SET_DATA GPIO Set Data Register
0x001C CLR_DATA GPIO Clear Data Register
0x0020 IN_DATA GPIO Input Data Register
0x0024 SET_RIS_TRIG GPIO Set Rising Edge Interrupt Register
0x0028 CLR_RIS_TRIG GPIO Clear Rising Edge Interrupt Register
0x002C SET_FAL_TRIG GPIO Set Falling Edge Interrupt Register
0x0030 CLR_FAL_TRIG GPIO Clear Falling Edge Interrupt Register
0x008C - Reserved
0x0090 – 0x03FF - Reserved

GPIO Electrical Data and Timing

The GPIO input timing requirements are shown in Table 11-54 and the GPIO output switching characteristics are shown in Table 11-55.

Table 11-54 GPIO Input Timing Requirements(1)

(see Figure 11-52)
NO. MIN MAX UNIT
1 tw(GPOH) Pulse duration, GPOx high 12C ns
2 tw(GPOL) Pulse duration, GPOx low 12C ns
C = 1/SYSCLK1 clock frequency in ns

Table 11-55 GPIO Output Switching Characteristics(1)

(see Figure 11-52)
NO. PARAMETER MIN MAX UNIT
3 tw(GPOH) Pulse duration, GPOx high 36C – 8 ns
4 tw(GPOL) Pulse duration, GPOx low 36C – 8 ns
C = 1/SYSCLK1 clock frequency in ns
66AK2H14 66AK2H12 66AK2H06 GPIO_Timing_NySh.gif Figure 11-52 GPIO Timing

Semaphore2

The device contains an enhanced Semaphore module for the management of shared resources of the SoC. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is not broken. The Semaphore module has unique interrupts to each of the CorePacs to identify when that CorePac has acquired the resource.

Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to allocate semaphore resources to the hardware resources to be arbitrated.

The Semaphore module supports all the CPUs in the device—12 for 66AK2H14 and 66AK2H12 devices, and 6 for 66AK2H06 devices—and contains 64 semaphores that can be shared within the system.

There are two methods of accessing a semaphore resource:

  • Direct Access: A C66x CorePac directly accesses a semaphore resource. If free, the semaphore is granted. If not free, the semaphore is not granted.
  • Indirect Access: A C66x CorePac indirectly accesses a semaphore resource by writing to it. Once the resource is free, an interrupt notifies the C66x CorePac that the resource is available.

Universal Serial Bus 3.0 (USB 3.0)

The device includes a USB 3.0 controller providing the following capabilities:

  • Support of USB 3.0 peripheral (or device) mode at the following speeds:
    • Super Speed (SS) (5 Gbps)
    • High Speed (HS) (480 Mbps)
    • Full Speed (FS) (12 Mbps)
  • Support of USB 3.0 host mode at the following speeds:
    • Super Speed (SS) (5 Gbps)
    • High Speed (HS) (480 Mbps)
    • Full Speed (FS) (12 Mbps)
    • Low Speed (LS) (1.5 Mbps)
  • Integrated DMA controller with extensible Host Controller Interface (xHCI) support
  • Support for 14 transmit and 14 receive endpoints plus control EP0

For more information, see the KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide.

EMIF16 Peripheral

The EMIF16 module provides an interface between the device and external memories such as NAND and NOR flash. For more information, see the KeyStone Architecture External Memory Interface (EMIF16) User's Guide.

EMIF16 Electrical Data and Timing

EMIF16 asynchronous memory timing requirements are shown in Table 11-56.

Table 11-56 EMIF16 Asynchronous Memory Timing Requirements(1)

(see Figure 11-53, Figure 11-54, Figure 11-55, and Figure 11-56)
NO. MIN MAX UNIT
General Timing
2 tw(WAIT) Pulse duration, WAIT assertion and deassertion minimum time 2E ns
28 td(WAIT-WEH) Setup time, WAIT asserted before WE high 4E + 3 ns
14 td(WAIT-OEH) Setup time, WAIT asserted before OE high 4E + 3 ns
Read Timing
3 tC(CEL) EMIF read cycle time when ew = 0, meaning not in extended wait mode (RS+RST+RH+3)*E-3 (RS+RST+RH+3)*E+3 ns
3 tC(CEL) EMIF read cycle time when ew =1, meaning extended wait mode enabled (RS+RST+RH+3)*E-3 (RS+RST+RH+3)*E+3 ns
4 tosu(CEL-OEL) Output setup time from CE low to OE low. SS = 0, not in select strobe mode (RS+1) × E – 3 (RS+1) × E + 3 ns
5 toh(OEH-CEH) Output hold time from OE high to CE high. SS = 0, not in select strobe mode (RH+1) × E – 3 (RH+1) × E + 3 ns
4 tosu(CEL-OEL) Output setup time from CE low to OE low in select strobe mode, SS = 1 (RS+1) × E – 3 (RS+1) × E + 3 ns
5 toh(OEH-CEH) Output hold time from OE high to CE high in select strobe mode, SS = 1 (RH+1) × E – 3 (RH+1) × E + 3 ns
6 tosu(BAV-OEL) Output setup time from BA valid to OE low (RS+1) × E – 3 (RS+1) × E + 3 ns
7 toh(OEH-BAIV) Output hold time from OE high to BA invalid (RH+1) × E – 3 (RH+1) × E + 3 ns
8 tosu(AV-OEL) Output setup time from A valid to OE low (RS+1) × E – 3 (RS+1) × E + 3 ns
9 toh(OEH-AIV) Output hold time from OE high to A invalid (RH+1) × E – 3 (RH+1) × E + 3 ns
10 tw(OEL) OE active time low, when ew = 0. Extended wait mode is disabled. (RST+1) × E – 3 (RST+1) × E + 3 ns
10 tw(OEL) OE active time low, when ew = 1. Extended wait mode is enabled. (RST+1) × E – 3 (RST+1) × E + 3 ns
11 td(WAITH-OEH) Delay time from WAIT deasserted to OE# high 4E + 3 ns
12 tsu(D-OEH) Input setup time from D valid to OE high 3 ns
13 th(OEH-D) Input hold time from OE high to D invalid 0.5 ns
Write Timing
15 tc(CEL) EMIF write cycle time when ew = 0, meaning not in extended wait mode (WS+WST+WH+TA+4)*E-3 (WS+WST+WH+TA+4)*E+3 ns
15 tc(CEL) EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WH+TA+4)*E-3 (WS+WST+WH+TA+4)*E+3 ns
16 tosuCEL-WEL) Output setup time from CE low to WE low. SS = 0, not in select strobe mode (WS+1) × E – 3 ns
17 toh(WEH-CEH) Output hold time from WE high to CE high. SS = 0, not in select strobe mode (WH+1) × E – 3 ns
16 tosuCEL-WEL) Output setup time from CE low to WE low in select strobe mode, SS = 1 (WS+1) × E – 3 ns
17 toh(WEH-CEH) Output hold time from WE high to CE high in select strobe mode, SS = 1 (WH+1) × E – 3 ns
18 tosu(RNW-WEL) Output setup time from RNW valid to WE low (WS+1) × E – 3 ns
19 toh(WEH-RNW) Output hold time from WE high to RNW invalid (WH+1) × E – 3 ns
20 tosu(BAV-WEL) Output setup time from BA valid to WE low (WS+1) × E – 3 ns
21 toh(WEH-BAIV) Output hold time from WE high to BA invalid (WH+1) × E – 3 ns
22 tosu(AV-WEL) Output setup time from A valid to WE low (WS+1) × E – 3 ns
23 toh(WEH-AIV) Output hold time from WE high to A invalid (WH+1) × E – 3 ns
24 tw(WEL) WE active time low, when ew = 0. Extended wait mode is disabled. (WST+1) × E – 3 ns
24 tw(WEL) WE active time low, when ew = 1. Extended wait mode is enabled. (WST+1) × E – 3 ns
26 tosu(DV-WEL) Output setup time from D valid to WE low (WS+1) × E – 3 ns
27 toh(WEH-DIV) Output hold time from WE high to D invalid (WH+1) × E – 3 ns
25 td(WAITH-WEH) Delay time from WAIT deasserted to WE# high 4E + 3 ns
E = 1/(SYSCLK1/6)
66AK2H14 66AK2H12 66AK2H06 EMIF16_Asynchronous_Memory_Read_Timing.gif Figure 11-53 EMIF16 Asynchronous Memory Read Timing Diagram
66AK2H14 66AK2H12 66AK2H06 EMIF16_Asynchronous_Memory_Write_Timing.gif Figure 11-54 EMIF16 Asynchronous Memory Write Timing Diagram
66AK2H14 66AK2H12 66AK2H06 EMIF16_EM_Wait_Read_Timing.gif Figure 11-55 EMIF16 EM_WAIT Read Timing Diagram
66AK2H14 66AK2H12 66AK2H06 EMIF16_EM_Wait_Write_Timing.gif Figure 11-56 EMIF16 EM_WAIT Write Timing Diagram

Emulation Features and Capability

The debug capabilities of KeyStone II devices include the Debug subsystem module (DEBUGSS). The DEBUGSS module contains the ICEPick module which handles the external JTAG Test Access Port (TAP) and multiple secondary TAPs for the various processing cores of the device. It also provides Debug Access Port (DAP) for system wide memory access from debugger, Cross triggering, System trace, Peripheral suspend generation, Debug port (EMUx) pin management, and so forth. The DEBUGSS module works in conjunction with the debug capability integrated in the processing cores (ARM and DSP subsystems) to provide a comprehensive hardware platform for a rich debug and development experience.

Chip-Level Features

  • Support for 1149.1(JTAG and Boundary scan) and 1149.6 (Boundary scan extensions).
  • Trace sources to DEBUG SubSystem System Trace Module (DEBUGSS STM)
    • Provides a way for hardware instrumentation and software messaging to supplement the processor core trace mechanisms.
    • Hardware instrumentation support of CPTracers to support logging of bus transactions for critical endpoints
    • Software messaging/instrumentation support for SoC and QMSS PDSP cores through DEBUGSS STM.
  • Trace Sinks
    • Support for trace export (from all processor cores and DEBUGSS STM) through emulation pins. Concurrent trace of DSP and STM traces or ARM and STM traces via EMU pins is possible. Concurrent trace export of DSP and ARM is not possible via EMU pins.
    • Support for 32KB DEBUGSS TBR (Trace Buffer and Router) to hold system trace. The data can be drained using EDMA to on-chip or DDR memory buffers. These intermediate buffers can subsequently be drained through the device high speed interfaces. The DEBUGSS TBR is dedicated to the DEBUGSS STM module. The trace draining interface used in KeyStone II for DEBUGSS and ARMSS are based on the new CT-TBR.
  • Cross triggering: Provides a way to propagate debug (trigger) events from one processor/subsystem/module to another
    • Cross triggering between multiple devices via EMU0/EMU1 pins
    • Cross triggering between multiple processing cores within the device like ARM/DSP Cores and nonprocessor entities like ARM STM (input only), CPTracers, CT-TBRs and DEBUGSS STM (input only)
  • Synchronized starting and stopping of processing cores
    • Global start of all DSP cores
    • Global stopping of all ARM and DSP cores
  • Emulation mode aware peripherals (suspend features and debug access features)
  • Support system memory access via the DAP port (natively support 32-bit address, and it can support 36-bit address through configuration of MPAX inside MSMC). Debug access to any invalid memory location (reserved/clock-gated/power-down) does not cause system hang.
  • Scan access to secondary TAPs of DEBUGSS is disabled in Secure devices by default. Security override sequence is supported (requires software override sequence) to enable debug in secure devices. In addition, Debug features of the ARM cores are blockable through the ARM debug authentication interface in secure devices.
  • Support WIR (wait-in-reset) debug boot mode for nonsecure devices.
  • Debug functionality survives all pin resets except power-on resets (POR/RESETFULL) and test reset (TRST).
  • PDSP Debug features like access/control through DAP, Halt mode debug and software instrumentation.

ARM Subsystem Features

  • Support for invasive debug like halt mode debugging (breakpoint, watchpoints) and monitor mode debugging
  • Support for noninvasive debugging (program trace, performance monitoring)
  • Support for A15 Performance Monitoring Unit (cycle counters)
  • Support for per core CoreSight Program Trace Module (CS-PTM) with timing
  • Support for an integrated CoreSight System Trace Module (CS-STM) for hardware event and software instrumentation
  • A shared timestamp counter for all ARM cores and STM is integrated in ARMSS for trace data correlation
  • Support for a 16KB Trace Buffer and Router (TBR) to hold PTM/STM trace. The trace data is copied by EDMA to external memory for draining by device high speed serial interfaces.
  • Support for simultaneous draining of trace stream through EMUn pins and TBR (to achieve higher aggregate trace throughput)
  • Support for debug authentication interface to disable debug accesses in secure devices
  • Support for cross triggering between MPU cores, CS-STM and CT-TBR
  • Support for debug through warm reset

DSP Features

  • Support for Halt-mode debug
  • Support for Real-time debug
  • Support for Monitor mode debug
  • Advanced Event Triggering (AET) for data/PC watch-points, event monitoring and visibility into external events
  • Support for PC/Timing/Data/Event trace.
  • TETB (TI Embedded Trace Buffer) of 4KB to store PC/Timing/Data/Event trace. The trace data is copied by EDMA to external memory for draining by device high speed serial interfaces or it can be drained through EMUx pins
  • Support for Cross triggering source/sink to other C66x CorePacs and device subsystems.
  • Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
  • Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems application report

For more information on the AET, see the following documents:

ICEPick Module

The debugger is connected to the device through its external JTAG interface. The first level of debug interface seen by the debugger is connected to the ICEPick module embedded in the DEBUGSS. ICEPick is the chip-level TAP, responsible for providing access to the IEEE 1149.1 and IEEE 1149.6 boundary scan capabilities of the device.

The device has multiple processors, some with secondary JTAG TAPs (C66x CorePacs) and others with an APB memory mapped interface (ARM CorePac and Coresight components). ICEPick manages the TAPs as well as the power/reset/clock controls for the logic associated with the TAPs as well as the logic associated with the APB ports.

ICEPick provides the following debug capabilities:

  • Debug connect logic for enabling or disabling most ICEPick instructions
  • Dynamic TAP insertion
    • Serially linking up to 32 TAP controllers
    • Individually selecting one or more of the TAPS for scan without disrupting the instruction register (IR) state of other TAPs
  • Power, reset and clock management
    • Provides the power and clock status of the domain to the debugger
    • Provides debugger control of the power domain of a processor.
      • Force the domain power and clocks on
      • Prohibit the domain from being clock-gated or powered down
    • Applies system reset
    • Provides wait-in-reset (WIR) boot mode
    • Provides global and local WIR release
    • Provides global and local reset block

The ICEPick module implements a connect register, which must be configured with a predefined key to enable the full set of JTAG instructions. Once the debug connect key has been properly programmed, ICEPick signals and subsystems emulation logic should be turned on.

ICEPick Dynamic Tap Insertion

To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP router to program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively choose which subsystem TAPs are accessible through the device-level debug interface. Each secondary TAP can be dynamically included in or excluded from the scan path. From external JTAG interface point of view, secondary TAPS that are not selected appear not to exist.

There are two types of components connected through ICEPick to the external debug interface:

  • Legacy JTAG Components — C66x implements a JTAG-compatible port and are directly interfaced with ICEPick and individually attached to an ICEPick secondary TAP.
  • CoreSight Components — The CoreSight components are interfaced with ICEPick through the CS_DAP module. The CS_DAP is attached to the ICEPick secondary TAP and translates JTAG transactions into APBv3 transactions.

Table 11-57 shows the ICEPick secondary taps in the system. For more details on the test related P1500 TAPs, see the DFTSS specification.

Table 11-57 ICEPick Debug Secondary TAPs

TAP # TYPE NAME IR SCAN LENGTH ACCESS IN SECURE DEVICE DESCRIPTION
0 n/a n/a n/a No Reserved (This is an internal TAP and not exposed at the DEBUGSS boundary)
1 JTAG C66x CorePac0 38 No C66x CorePac0
2 JTAG C66x CorePac1 38 No C66x CorePac1
3 JTAG C66x CorePac2 38 No C66x CorePac2
4 JTAG C66x CorePac3 38 No C66x CorePac3
5 JTAG C66x CorePac4 38 No C66x CorePac4 (66AK2H12/14 only)
6 JTAG C66x CorePac5 38 No C66x CorePac5 (66AK2H12/14 only)
7 JTAG C66x CorePac6 38 No C66x CorePac6 (66AK2H12/14 only)
8 JTAG C66x CorePac7 38 No C66x CorePac7 (66AK2H12/14 only)
9..13 JTAG Reserved NA No Spare ports for future expansion
14 CS CS_DAP (APB-AP) 4 No ARM A15 Cores (This is an internal TAP and not exposed at the DEBUGSS boundary)
CS_DAP (AHB-AP) PDSP Cores (This is an internal TAP and not exposed at the DEBUGSS boundary)

For more information on ICEPick, see the KeyStone II Architecture Debug and Trace User’s Guide.

Debug Port (EMUx)

The device also supports 34 emulation pins — EMU[33:0], which includes 19 dedicated EMU pins and 15 pins multiplexed with GPIO. These pins are shared by A15/DSP/STM trace, cross triggering, and debug boot modes as shown in Table 11-61. The 34-pin dedicated emulation interface is also defined in the following table.

NOTE

If EMU[1:0] signals are shared for cross-triggering purposes in the board level, they should not be used for trace purposes.

Table 11-58 Emulation Interface with Different Debug Port Configurations

EMU PINS CROSS TRIGGERING ARM TRACE DSP TRACE STM DEBUG BOOT MODE
EMU33 TRCDTa[29] TRCDTb[31] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or Hi-ZTRCCLK, or Hi-Z
EMU32 TRCDTa[28] TRCDTb[30] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU31 TRCDTa[27] TRCDTb[29] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU30 TRCDTa[26] TRCDTb[28] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU29 TRCDTa[25] TRCDTb[27] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU28 TRCDTa[24] TRCDTb[26] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU27 TRCDTa[23] TRCDTb[25] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU26 TRCDTa[22] TRCDTb[24] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU25 TRCDTa[21] TRCDTb[23] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU24 TRCDTa[20] TRCDTb[22] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU23 TRCDTa[19] TRCDTb[21] TRCDTa[19] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU22 TRCDTa[18] TRCDTb[20] TRCDTa[18] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU21 TRCDTa[17] TRCDTb[19] TRCDTa[17] TRCDTb[19] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU20 TRCDTa[16] TRCDTb[18] TRCDTa[16] TRCDTb[18] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU19 TRCDTa[15] TRCDTb[17] TRCDTa[15] TRCDTb[17] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU18 TRCDTa[14] TRCDTb[16] TRCDTa[14] TRCDTb[16] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU17 TRCDTa[13] TRCDTb[15] TRCDTa[13] TRCDTb[15] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU16 TRCDTa[12] TRCDTb[14] TRCDTa[12] TRCDTb[14] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU15 TRCDTa[11] TRCDTb[13] TRCDTa[11] TRCDTb[13] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU14 TRCDTa[10] TRCDTb[12] TRCDTa[10] TRCDTb[12] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU13 TRCDTa[9] TRCDTb[11] TRCDTa[9] TRCDTb[11] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU12 TRCDTa[8] TRCDTb[10] TRCDTa[8] TRCDTb[10] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU11 TRCDTa[7] TRCDTb[9] TRCDTa[7] TRCDTb[9] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU10 TRCDTa[6] TRCDTb[8] TRCDTa[6] TRCDTb[8] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU9 TRCDTa[5] TRCDTb[7] TRCDTa[5] TRCDTb[7] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU8 TRCDTa[4] TRCDTb[6] TRCDTa[4] TRCDTb[6] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU7 TRCDTa[3] TRCDTb[5] TRCDTa[3] TRCDTb[5] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU6 TRCDTa[2] TRCDTb[4] TRCDTa[2] TRCDTb[4] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU5 TRCDTa[1] TRCDTb[3] TRCDTa[1] TRCDTb[3] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU4 TRCDTa[0] TRCDTb[2] TRCDTa[0] TRCDTb[2] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU3 TRCCTRL TRCCTRL TRCCLKB TRCCLKB TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU2 TRCCLK TRCCLK TRCCLKA TRCCLKA TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z
EMU1 Trigger1 TRCDTb[1] TRCDTb[1] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z dbgbootmode[1]
EMU0 Trigger0 TRCDTb[0] TRCDTb[0] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Hi-Z dbgbootmode[0]

Concurrent Use of Debug Port

The following combinations are possible concurrently:

  • Trigger 0/1
  • Trigger 0/1 and STM Trace (up to 4 data pins)
  • Trigger 0/1 and STM Trace (up to 4 data pins) and C66x Trace (up to 20 data pins)
  • Trigger 0/1 and STM Trace (1-4 data pins) and ARM Trace (27-24 data pins)
  • STM Trace (1-4 data pins) and ARM Trace (29-26 data pins)
  • Trigger 0/1 and ARM Trace (up to 29 data pins)
  • ARM Trace (up to 32 data pins)

ARM and DSP simultaneous trace is not supported.

Master ID for Hardware and Software Messages

Table 11-59 and Table 11-60 describe the master ID for the various hardware and software masters of the STM.

Table 11-59 MSTID Mapping for Hardware Instrumentation (CPTRACERS)

CPTRACER NAME MSTID [7:0] CLOCK DOMAIN SID[4:0] DESCRIPTION
CPT_MSMCx_MST, where x = 0..3 0x94-0x97 SYSCLK1/1 0x0..3 MSMC SRAM Bank 0 to MSMC SRAM Bank 3 monitors
CPT_MSMC4_MST 0xB1 SYSCLK1/1 0x4 MSMC SRAM Bank 4
CPT_MSMCx_MST, where x = 5..7 0xAE – 0xB0 SYSCLK1/1 0x5..7 MSMC SRAM Bank 5to MSMC SRAM Bank 7 monitors
CPT_DDR3A_MST 0x98 SYSCLK1/1 0x8 MSMC DDR3A port monitor
CPT_L2_x_MST, where x = 0..7 0x8C – 0x93 SYSCLK1/3 0x9..0x10 DSP 0 to 7 SDMA port monitors
CPT_TPCC0_4_MST 0xA4 SYSCLK1/3 0x11 EDMA 0 and EDMA 4 CFG port monitor
CPT_TPCC1_2_3_MST 0xA5 SYSCLK1/3 0x12 EDMA 1, EDMA2 and EDMA3 CFG port monitor
CPT_INTC_MST 0xA6 SYSCLK1/3 0x13 INTC port monitor (for INTC 0/1/2 and GIC400)
CPT_SM_MST 0x99 SYSCLK1/3 0x14 Semaphore CFG port monitors
CPT_QM_CFG1_MST 0x9A SYSCLK1/3 0x15 QMSS CFG1 port monitor
CPT_QM_CFG2_MST 0xA0 SYSCLK1/3 0x16 QMSS CFG2 port monitor
CPT_QM_M_MST 0x9B SYSCLK1/3 0x17 QM_M CFG/DMA port monitor
CPT_SPI_ROM_EMIF16_MST 0xA7 SYSCLK1/3 0x18 SPI ROM EMIF16 CFG port monitor
CPT_CFG_MST 0x9C SYSCLK1/3 0x19 SCR_3P_B and SCR_6P_B CFG peripheral port monitors
Reserved 0x1A Reserved
Reserved 0x1B Reserved
Reserved 0x1C Reserved
Reserved 0x1D Reserved
Reserved 0x1E Reserved
CPT_DDR3B_MST 0xA1 SYSCLK1/3 0x1F DDR 3B port monitor (on SCR 3C)

Table 11-60 MSTID Mapping for Software Messages

CORE NAME MSTID [7:0] DESCRIPTION
C66x CorePac0 0x0 C66x CorePac MDMA Master ID
C66x CorePac1 0x1 C66x CorePac MDMA Master ID
C66x CorePac2 0x2 C66x CorePac MDMA Master ID
C66x CorePac3 0x3 C66x CorePac MDMA Master ID
C66x CorePac4 0x4 (66AK2H14/12 only)
C66x CorePac5 0x5 (66AK2H14/12 only)
C66x CorePac6 0x6 (66AK2H14/12 only)
C66x CorePac7 0x7 (66AK2H14/12 only)
A15 Core0 0x8 ARM Master IDs
A15 Core1 0x9 ARM Master ID
A15 Core2 0xA ARM Master ID
A15 Core3 0xB ARM Master ID
QMSS PDSPs 0x46 All QMSS PDSPs share the same master ID. Differentiating between the 8 PDSPs is done through the channel number used

SoC Cross-Triggering Connection

The cross-trigger lines are shared by all the subsystems implementing cross-triggering. An MPU subsystem trigger event can therefore be propagated to any application subsystem or system trace component. The remote subsystem or system trace component can be programmed to be sensitive to the global SOC trigger lines to either:

  • Generate a processor debug request
  • Generate an interrupt request
  • Start/Stop processor trace
  • Start/Stop CBA transaction tracing through CPTracers
  • Start external logic analyzer trace
  • Stop external logic analyzer trace

Table 11-61 describes the cross-triggering connection.

Table 11-61 Cross-Triggering Connection

NAME SOURCE TRIGGERS SINK TRIGGERS COMMENTS
Inside DEBUGSS
Device-to-device trigger via EMU0/1 pins YES YES This is fixed (not affected by configuration)
MIPI-STM NO YES Trigger input only for MIPI-STM in DebugSS
CT-TBR YES YES DEBUGSS CT-TBR
CS-TPIU NO YES DEBUGSS CS-TPIU
Outside DEBUGSS
DSPSS YES YES
CP_Tracers YES YES
ARM YES YES ARM Cores, ARM CS-STM and ARM CT-TBR

Table 11-62 describes the crosstrigger connection between various cross trigger sources and TI XTRIG module.

Table 11-62 TI XTRIG Assignment

NAME ASSIGNED XTRIG CHANNEL NUMBER
C66x CorePac0-3 (66AK2H06 only) XTRIG 0-3 (66AK2H06 only)
C66x CorePac0-7 (66AK2H12/14 only) XTRIG 0-7 (66AK2H12/14 only)
CPTracer 0..31 (The CPTracer number refers to the SID[4:0] as shown in Table 11-59 XTRIG 8 .. 39

Peripherals-Related Debug Requirement

Table 11-63 lists all the peripherals on this device, and the status of whether or not it supports emulation suspend or emulation request events.

The DEBUGSS supports up to 32 debug suspend sources (processor cores) and 64 debug suspend sinks (peripherals). The assignment of peripherals is shown in Table 11-64 and the assignment of processor cores is shown in Table 11-65. By default the logical AND of all the processor cores is routed to the peripherals. It is possible to select an individual core to be routed to the peripheral (For example: used in tightly coupled peripherals like timers), a logical AND of all cores (Global peripherals) or a logical OR of all cores by programming the DEBUGSS.DRM module.

The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral function is required or if the peripheral suspend should occur only after a particular completion point is reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the emulation suspend functionality.

Table 11-63 Peripherals Emulation Support

PERIPHERAL EMULATION SUSPEND SUPPORT EMULATION REQUEST SUPPORT (cemudbg/emudbg) DEBUG PERIPHERAL ASSIGNMENT
STOP-MODE REAL-TIME MODE FREE BIT STOP BIT
Infrastructure Peripherals
EDMA_x, where X=0/1/2/3/4 N N N N Y NA
QM_SS Y (CPDMA only) Y (CPDMA only) Y (CPDMA only) Y (CPDMA only) Y 20
CP_Tracers_X, where X = 0..32 N N N N N NA
MPU_X, where X = 0..11 N N N N Y NA
CP_INTC N N N N Y NA
BOOT_CFG N N N N Y NA
SEC_MGR N N N N Y NA
PSC N N N N N NA
PLL N N N N N NA
TIMERx, x=0, 1..7, 8..19 Y N Y Y N 0, 1..7, 8..19
Semaphore N N N N Y NA
GPIO N N N N N NA
Memory Controller Peripherals
DDR3A/B N N N N Y NA
MSMC N N N N Y NA
EMIF16 N N N N Y NA
Serial Interfaces
I2C_X, where X = 0/1/2 Y N Y Y Y 21/22/23
SPI_X, where X = 0/1/2 N N N N Y NA
UART_X, where X = 0/1 Y N Y Y Y 24/25
High Speed Serial Interfaces
Hyperlink_0/1 N N N N Y
PCIeSS 0 N N N N N
SRIO / NetCP_1 Y Y Y Y (Soft Only) Y 26
NetCP (ethernet switch) Y Y Y Y N 27
10GbE (ethernet switch)(1) Y N Y Y N 29
USBSS N N N N N NA
66AK2H14 only

Based on Table 11-63, the number of suspend interfaces in Keystone II devices is listed in Table 11-64.

Table 11-64 EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS)

INTERFACES NUM_SUSPEND_PERIPHERALS
EMUSUSP Interfaces 54
EMUSUSP Realtime Interfaces 15

Table 11-65 summarizes the DEBUG core assignment. Emulation suspend output of all the cores are synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.

Table 11-65 EMUSUSP Core Summary (for EMUSUSP handshake to DEBUGSS)

CORE # ASSIGNMENT
0..7 C66x CorePac0..7
8..11 ARM CorePac 8..11
0..7 C66x CorePac0..3

C66x CorePac4.,7 (66AK2H12/14 only)

12..29 Reserved
30 Logical OR of Core# 0..11
31 Logical AND of Core #0..11

Advanced Event Triggering (AET)

The device supports advanced event triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities:

  • Hardware program breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.
  • Data watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture.
  • Counters: count the occurrence of an event or cycles for performance monitoring.
  • State sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.

For more information on the AET, see the following documents:

Trace

The device supports trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system.

For more information on board design guidelines for trace advanced emulation, see the Emulation and Trace Headers Technical Reference Manual.

Trace Electrical Data and Timing

The Trace switching characteristics are shown in Table 11-66.

Table 11-66 Trace Switching Characteristics

(see Figure 11-57)
NO. PARAMETER MIN MAX UNIT
1 tw(DPnH) Pulse duration, DPn/EMUn high 2.4 ns
1 tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh 1.5 ns
2 tw(DPnL) Pulse duration, DPn/EMUn low 2.4 ns
2 tw(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh 1.5 ns
3 tsko(DPn) Output skew time, time delay difference between DPn/EMUn pins configured as trace -1 1 ns
tskp(DPn) Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays. 600 ps
tsldp_o(DPn) Output slew rate DPn/EMUn 3.3 V/ns
66AK2H14 66AK2H12 66AK2H06 Trace_Timing.gif Figure 11-57 Trace Timing

IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous test reset (TRST) and only the five baseline JTAG signals (for example, no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE 1149.1), while all of the SerDes (SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE 1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).

IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the 66AK2Hxx device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device’s internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high, but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

JTAG Electrical Data and Timing

JTAG test port timing requirements are shown in Table 11-67 and JTAG test port switching characteristics are shown in Table 11-68.

Table 11-67 JTAG Test Port Timing Requirements

(see Figure 11-58)
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 23 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 9.2 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 9.2 ns
3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high 2 ns
3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high 2 ns
4 th(TCK-TDI) Input hold time, TDI valid from TCK high 10 ns
4 th(TCK-TMS) Input hold time, TMS valid from TCK high 10 ns

Table 11-68 JTAG Test Port Switching Characteristics

(see Figure 11-58)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 8.24 ns
66AK2H14 66AK2H12 66AK2H06 JTAG_Test-Port_Timing_NySh.gif Figure 11-58 JTAG Test-Port Timing