SNAS518J July   2011  – July 2015 ADC12D1800RF


  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Functions
  4. Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 4.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 4.7  Converter Electrical Characteristics: Analog Input / Output and Reference Characteristics
    8. 4.8  Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics
    9. 4.9  Converter Electrical Characteristics: Sampling Clock Characteristics
    10. 4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics
    11. 4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 4.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 4.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 4.14 Converter Electrical Characteristics: Serial Port Interface
    15. 4.15 Converter Electrical Characteristics Calibration
    16. 4.16 Typical Characteristics
  5. Detailed Description
    1. 5.1 Overview
      1. 5.1.1 RF Performance
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. AC/DC-coupled Mode
        2. Input Full-Scale Range Adjust
        3. Input Offset Adjust
        4. DES Timing Adjust
        5. Sampling Clock Phase (Aperture) Delay Adjust
      2. 5.3.2 Output Control and Adjust
        1. SDR / DDR Clock
        2. LVDS Output Differential Voltage
        3. LVDS Output Common-Mode Voltage
        4. Output Formatting
        5. Test Pattern Mode
        6. Time Stamp
      3. 5.3.3 Calibration Feature
        1. Calibration Control Pins and Bits
        2. How to Execute a Calibration
        3. Power-on Calibration
        4. On-command Calibration
        5. Calibration Adjust
        6. Read / Write Calibration Settings
        7. Calibration and Power-Down
        8. Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES/Non-DES Mode
      2. 5.4.2 Demux/Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. Non-Extended Control Mode
          1.  Dual Edge Sampling Pin (DES)
          2.  Non-Demultiplexed Mode Pin (NDM)
          3.  Dual Data Rate Phase Pin (DDRPh)
          4.  Calibration Pin (CAL)
          5.  Calibration Delay Pin (CalDly)
          6.  Power Down I-channel Pin (PDI)
          7.  Power Down Q-channel Pin (PDQ)
          8.  Test Pattern Mode Pin (TPM)
          9.  Full-Scale Input Range Pin (FSR)
          10. AC / DC-Coupled Mode Pin (VCMO)
          11. LVDS Output Common-mode Pin (VBG)
        2. Extended Control Mode
          1. The Serial Interface
    6. 5.6 Register Maps
      1. 5.6.1 Register Definitions
  6. Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Analog Inputs
        1. Acquiring the Input
        2. Driving the ADC in DES Mode
        3. FSR and the Reference Voltage
        4. Out-of-Range Indication
        5. Maximum Input Range
        6. AC-Coupled Input Signals
        7. DC-Coupled Input Signals
        8. Single-Ended Input Signals
      2. 6.1.2 Clock Inputs
        1. CLK Coupling
        2. CLK Frequency
        3. CLK Level
        4. CLK Duty Cycle
        5. CLK Jitter
        6. CLK Layout
      3. 6.1.3 LVDS Outputs
        1. Common-mode and Differential Voltage
        2. Output Data Rate
        3. Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1800RFS in a System
        1. AutoSync Feature
        2. DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. Temperature Sensor
        2. Clocking Device
        3. Amplifiers for Analog Input
        4. Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 RF Sampling Receiver
      2. 6.2.2 Design Requirements
      3. 6.2.3 Detailed Design Procedure
      4. 6.2.4 Application Curves
  7. Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
  8. Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Specification Definitions
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information



9 Device and Documentation Support

9.1 Device Support

9.1.1 Specification Definitions

APERTURE JITTER (tAJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be effectively considered as noise at the input.

CODE ERROR RATE (CER) is the probability of error and is defined as the probable number of word errors on the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10-18 corresponds to a statistical error in one word about every 31.7 years.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. It is measured at the relevant sample rate, fCLK, with fIN = 1MHz sine wave.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this many (ENOB) number of bits.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and Full-Scale Errors. The Positive Gain Error is the Offset Error minus the Positive Full-Scale Error. The Negative Gain Error is the Negative Full-Scale Error minus the Offset Error. The Gain Error is the Negative Full-Scale Error minus the Positive Full-Scale Error; it is also equal to the Positive Gain Error plus the Negative Gain Error.

GAIN FLATNESS is the measure of the variation in gain over the specified bandwidth. For example, for the ADC12D1800RF, from D.C. to Fs/2 is to 900 MHz for the Non-DES Mode and from D.C. to Fs/2 is 1800 MHz for the DES Mode.

INTEGRAL NON-LINEARITY (INL) is a measure of worst case deviation of the ADC transfer function from an ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line is measured from the center of that code value step. The best fit method is used.

INSERTION LOSS is the loss in power of a signal due to the insertion of a device, e.g. the ADC12D1800RF, expressed in dB.

INTERMODULATION DISTORTION (IMD) is a measure of the near-in 3rd order distortion products (2f2 - f1, 2f1 - f2) which occur when two tones which are close in frequency (f1, f2) are applied to the ADC input. It is measured from the input tones level to the higher of the two distortion products (dBc) or simply the level of the higher of the two distortion products (dBFS). The input tones are typically -7dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is

Equation 1. VFS / 2N

where VFS is the differential full-scale amplitude VIN_FSR as set by the FSR input and "N" is the ADC resolution in bits, which is 12 for the ADC12D1800RF.

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is two times the absolute value of the difference between the VD+ and VD- signals; each signal measured with respect to Ground. VOD peak is VOD,P= (VD+ - VD-) and VOD peak-to-peak is VOD,P-P= 2*(VD+ - VD-); for this product, the VOD is measured peak-to-peak.

ADC12D1800RF 30164346.gifFigure 9-1 LVDS Output Signal Levels

LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D- pins output voltage with respect to ground; i.e., [(VD+) +( VD-)]/2. See Figure 9-1.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2 LSB above a differential −VIN/2. For the ADC12D1800RF the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.

NOISE FLOOR DENSITY is a measure of the power density of the noise floor, expressed in dBFS/Hz and dBm/Hz. '0 dBFS' is defined as the power of a sinusoid which precisely uses the full-scale range of the ADC.

NOISE POWER RATIO (NPR) is the ratio of the sum of the power outside the notched bins to the sum of the power in an equal number of bins inside the notch, expressed in dB.

OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input.

Offset Error = Actual Input causing average of 8k samples to result in an average code of 2047.5.

OUTPUT DELAY (tOD) is the time delay (in addition to Latency) after the rising edge of CLK+ before the data update is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2V to 0V for the converter to recover and make a conversion with its rated accuracy.

PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when that data is presented to the output driver stage. The data lags the conversion by the Latency plus the tOD.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2 LSB below a differential +VIN/2. For the ADC12D1800RF the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental for a single-tone to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the fundamental for a single-tone to the rms value of all of the other spectral components below half the input clock frequency, including harmonics but excluding DC.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC.

θJA is the thermal resistance between the junction to ambient.

θJC1 represents the thermal resistance between the die and the exposed metal area on the top of the HSBGA package.

θJC2 represents the thermal resistance between the die and the center group of balls on the bottom of the HSBGA package.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as

Equation 2. ADC12D1800RF 30164305.gif


    Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in its 2nd harmonic level at the output.

    Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic level at the output.

    9.1.2 Third-Party Products Disclaimer


    9.2 Documentation Support

    9.2.1 Related Documentation

    AN-1126 BGA (Ball Grid Array) , SNOA021

    AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature, SNAA073

    9.3 Community Resources

    The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

      TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
      Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

    9.4 Trademarks

    E2E is a trademark of Texas Instruments.

    All other trademarks are the property of their respective owners.

    9.5 Electrostatic Discharge Caution


    These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

    9.6 Glossary

    SLYZ022TI Glossary.

    This glossary lists and explains terms, acronyms, and definitions.