SNAS518J July 2011 – July 2015 ADC12D1800RF
There are a couple important topics to consider associated with the system power-on event including configuration and calibration, and the Data Clock.
Following the application of power to the ADC12D1800RF, several events must take place before the output from the ADC12D1800RF is valid and at full performance; at least one full calibration must be executed with the device configured in the desired mode.
Following the application of power to the ADC12D1800RF, there is a delay of tCalDly and then the Power-on Calibration is executed. This is why it is recommended to set the CalDly Pin via an external pull-up or pull-down resistor. This ensured that the state of that input will be properly set at the same time that power is applied to the ADC and tCalDly will be a known quantity. For the purpose of this section, it is assumed that CalDly is set as recommended.
The Control Bits or Pins must be set or written to configure the ADC12D1800RF in the desired mode. This must take place via either Extended Control Mode or Non-ECM (Pin Control Mode) before subsequent calibrations will yield an output at full performance in that mode. Some examples of modes include DES/Non-DES Mode, Demux/Non-demux Mode, and Full-Scale Range.
The simplest case is when device is in Non-ECM and the Control Pins are set by pull-up / down resistors, see Figure 7-1. For this case, the settings to the Control Pins ramp concurrently to the ADC voltage. Following the delay of tCalDly and the calibration execution time, tCAL, the output of the ADC12D1800RF is valid and at full performance. If it takes longer than tCalDly for the system to stabilize at its operating temperature, it is recommended to execute an on-command calibration at that time.
Another case is when the FPGA configures the Control Pins (Non-ECM) or writes to the SPI (ECM), see Figure 7-2. It is always necessary to comply with the Operating Ratings and Absolute Maximum ratings, i.e. the Control Pins may not be driven below the ground or above the supply, regardless of what the voltage currently applied to the supply is. Therefore, it is not recommended to write to the Control Pins or SPI before power is applied to the ADC12D1800RF. As long as the FPGA has completed writing to the Control Pins or SPI, the Power-on Calibration will result in a valid output at full performance. Once again, if it takes longer than tCalDly for the system to stabilize at its operating temperature, it is recommended to execute an on-command calibration at that time.
Due to system requirements, it may not be possible for the FPGA to write to the Control Pins or SPI before the Power-on Calibration takes place, see Figure 7-3. It is not critical to configure the device before the Power-on Calibration, but it is critical to realize that the output for such a case is not at its full performance. Following an On-command Calibration, the device will be at its full performance.
Many applications use the DCLK output for a system clock. For the ADC12D1800RF, each I- and Q-channel has its own DCLKI and DCLKQ, respectively. The DCLK output is always active, unless that channel is powered-down or the DCLK Reset feature is used while the device is in Demux Mode. As the supply to the ADC12D1800RF ramps, the DCLK also comes up, see this example from the ADC12D1800RFRB: Figure 7-4. While the supply is too low, there is no output at DCLK. As the supply continues to ramp, DCLK functions intermittently with irregular frequency, but the amplitude continues to track with the supply. Much below the low end of operating supply range of the ADC12D1800RF, the DCLK is already fully operational.