JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores. Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the low-power background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is an increase in power consumption during the ADC core calibration. The power consumption roughly alternates between the power consumption in foreground calibration when the spare ADC core is sleeping to the power consumption in background calibration when the spare ADC is being calibrated. Design the power-supply network to handle the transient power requirements for this mode.