JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write (R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with respect to the SCLK must be observed (see the Timing Requirements table).