JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
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Clock Control 0 (default: 0x00)
This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.
Set this bit to enable the SYSREF receiver circuit (default: disabled)
Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.
Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. These bits must be set to 0 to use SYSREF calibration; see the Automatic SYSREF Calibration section.