0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer clocks). Use this mode to transmit data from the extra lanes.
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp (same as JTEST=4).
4. This register doesn’t override the PD_CH register, so ensure that the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.