8.6.52 OVR_T0 Register (Address = 0x211) [reset = 0x0]
OVR_T0 is shown in Figure 75 and described in Table 111.
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Over-range Threshold 0 (default: 0xF2)
Figure 75. OVR_T0 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
OVR_T0 |
R/W-0x0 |
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Table 111. OVR_T0 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7:0 |
OVR_T0 |
R/W |
0x0 |
This parameter defines the absolute sample level that causes control bit 0 to be set. Control bit 0 is attached to the DDC I output samples. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (Default: 0xF2 = 242-> -0.5dBFS)
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