JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
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Alarm Status (default: 0x3F, write to clear)
FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM.
PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked. Write a ‘1’ to clear this bit.
Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the data encoder state (for 8B/10B modes). In 64B/66B modes, there is no data encoder state, so this alarm will be set when the link first starts up, and will also be set if any event causes a FIFO/serializer realignment. Write a ‘1’ to clear this bit.
Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit.
NCO Alarm: This bit can be used to detect an upset to the NCO phase. This bit is set when any of the following occur:
Clock Alarm: This bit can be used to detect an upset to the internal DDC/JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.