8.6.86 TADJ_A Register (Address = 0x310) [reset = 0x0]
TADJ_A is shown in Figure 109 and described in Table 145.
Return to Summary Table.
Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)
Figure 109. TADJ_A Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
TADJ_A |
R/W-0x0 |
|
Table 145. TADJ_A Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7:0 |
TADJ_A |
R/W |
0x0 |
This register (and other TADJ* registers that follow it) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes. The default values for all TADJ* registers are factory programmed values. The factory trimmed values can be read out and adjusted as required.
|