JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices achieve the same deterministic latency then they can be considered synchronized. This latency must be achieved from system startup to startup to be deterministic. There are two key requirements to achieve deterministic latency. The first is proper capture of SYSREF for which the ADC12DJ5200RF provides a number of features to simplify this requirement at giga-sample clock rates (see the SYSREF Capture for Multi-Device Synchronization and Deterministic Latency section for more information). SYSREF resets either the LMFC in 8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC and LEMC are analogous between the two modes and will now be referred to as LMFC/LEMC.
The second requirement is to choose a proper elastic buffer release point in the receiver. Because the ADC12DJ5200RF is an ADC, the ADC12DJ5200RF is the transmitter (TX) in the JESD204C link and the logic device is the receiver (RX). The elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency variation of one LMFC/LEMC period. Choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total expected delay variation for all devices. With this information the region of invalid release points within the LMFC/LEMC period can be defined, which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must ensure that the data for all lanes arrives at all devices after the previous release point occurs and before the next release point occurs.
Figure 18 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is shown. The second ADC has a longer routing distance (tPCB) and results in a longer link delay. First, the invalid region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the LMFC/LEMC cycle. In the case of Figure 18, the LMFC/LEMC edge (RBD = 0) is a good choice for the release point because there is sufficient margin on each side of the valid region.
The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the requirements for more information.