JAJSEG5A January 2018 – October 2018 ADS112U04
The device features programmable gains of 1, 2, 4, 8, 16, 32, 64, and 128. Three bits (GAIN[2:0]) in the configuration register are used to configure the gain. Gains are achieved in two stages. The first stage is a low-noise, low-drift, high input impedance, programmable gain amplifier (PGA). The second gain stage is implemented by a switched-capacitor circuit at the input to the ΔΣ modulator. Table 9 shows how each gain is implemented.
|GAIN SETTING||PGA GAIN||SWITCHED-CAPACITOR GAIN|
The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the PGA gain. The input is equipped with an electromagnetic interference (EMI) filter. Figure 46 shows a simplified diagram of the PGA.
VIN denotes the differential input voltage VIN = VAINP – VAINN. Use Equation 4 to calculate the gain of the PGA. Gain is changed inside the device using a variable resistor, RG.
The switched-capacitor gain is changed using variable capacitors at the input to the ΔΣ modulator. Gains 1, 2, and 4 are implemented by using only the switched-capacitor circuit, which allows these gains to be used even when the PGA is bypassed; see the Bypassing the PGA section for more information about bypassing the PGA.
Equation 5 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain setting and the reference voltage used:
Table 10 shows the corresponding full-scale ranges when using the internal 2.048-V reference.