JAJSEG5A January 2018 – October 2018 ADS112U04
DRDY indicates when a new conversion result is ready for retrieval. The DRDY signal appears on the GPIO2/DRDY pin only when GPIO2 is configured as an output and the GPIO2SEL bit in the configuration register is set. When DRDY falls low, new conversion data are ready. DRDY transitions back high when the conversion result is latched for output transmission. In case a conversion result in continuous conversion mode is not read (only applies to manual data read mode), DRDY pulses high for tw(DRH) before the next conversion completes; see the UART Switching Characteristics section for more details.