JAJSGG2C October 2018 – June 2019 ADS125H02
A key consideration in the design of an analog input module is the error over the ambient temperature range resulting from the drift of gain, offset, reference voltage, and linearity error. This example assumes the initial offset and gain (including reference voltage error) are user calibrated at TA = 25°C. Table 47 shows the maximum drift error of the ADC over the 0°C to +105°C temperature range.
|PARAMETER||ERROR (0°C TO +105°C)|
|Offset drift error||0.00125%|
|Gain drift error||0.032%|
|Linearity error (over temperature)||0.001%|
|Reference drift error||ADS125H02 internal reference||0.16%|
|REF5025IDGK external reference||0.024%|
|Total drift error||ADS125H02 internal reference||0.19425%|
|REF5025IDGK external reference||0.05825%|
As shown in Table 47, the largest error is from the internal voltage reference. The reference drift error is improved by using the REF5025IDGK external reference. Using the external reference, the total drift error is 0.05825%, which satisfies the 0.1% total error design goal.
The ADC gain is programmed to 0.1875. With a 2.5-V reference voltage, the ADC input range is ±2.5 V / 0.1875 = ±13.3 V. However, using ±15-V power supplies, the required headroom of the PGA limits the range to ±12.5 V (which excludes the tolerance of the ±15-V power supplies). The input range satisfies the extended range design target of ±12 V.
The 1-GΩ minimum input impedance of the ADC and the 100-MΩ external pullup resistor meets the input impedance goal of 100 MΩ. The input fault overvoltage requirement (35 V) is met by limiting the ADC input current to 10 mA. The external 5-kΩ input resistor limits the input current to 7 mA.
The data rate that meets the continuos conversion, 50-µs acquisition period is 25600 SPS (39 µs actual). If a precise 50-µs conversion period is desired, reduce the clock frequency to the ADC with an external clock source. The clock frequency that yields a 50-µs conversion period is 5.76 MHz.
Table 1 lists noise performance data under all combinations of gain, sample rate, and digital filter order. The specified conversion noise for the ADC configuration in this example is 100 µVRMS. The effective resolution is derived by Equation 1, and calculates to: 3.32 log (26.6 V / 100 µV) = 18 bits.