JAJSGG2C October   2018  – June 2019 ADS125H02


  1. 特長
  2. アプリケーション
  3. 概要
    1.     機能ブロック図
  4. 改訂履歴
  5. 概要(続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. Parameter Measurement Information
    1. 9.1 Noise Performance
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Range
      2. 10.3.2 Analog Inputs
        1. ESD Diodes
        2. Input Multiplexer
          1. Analog Inputs (AIN0, AIN1, AINCOM)
          2. High-Voltage Power Supply Readback
          3. Internal VCOM Connection (Default)
          4. Temperature Sensor
      3. 10.3.3 Programmable Gain Amplifier (PGA)
        1. PGA Operating Range
        2. PGA Monitor
      4. 10.3.4 Reference Voltage
        1. Internal Reference
        2. External Reference
        3. AVDD Power-Supply Reference
        4. Reference Monitor
      5. 10.3.5 Current Sources (IDAC1 and IDAC2)
      6. 10.3.6 General-Purpose Inputs and Outputs (GPIOs)
      7. 10.3.7 ADC Modulator
      8. 10.3.8 Digital Filter
        1. Sinc Filter Mode
          1. Sinc Filter Frequency Response
        2. FIR Filter
        3. 50-Hz and 60-Hz Normal Mode Rejection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Conversion Control
        1. Continuous-Conversion Mode
        2. Pulse-Conversion Mode
        3. Conversion Latency
        4. Start-Conversion Delay
      2. 10.4.2 Auto-Zero Mode
      3. 10.4.3 Clock Mode
      4. 10.4.4 Reset
        1. Power-On Reset
        2. Reset by Pin
        3. Reset by Command
      5. 10.4.5 Calibration
        1. Offset and Full-Scale Calibration
          1. Offset Calibration Registers
          2. Full-Scale Calibration Registers
        2. Offset Calibration (OFSCAL)
        3. Full-Scale Calibration (GANCAL)
        4. Calibration Command Procedure
        5. User Calibration Procedure
    5. 10.5 Programming
      1. 10.5.1 Serial Interface
        1. Chip-Select Pins (CS1 and CS2)
        2. Serial Clock (SCLK)
        3. Data Input (DIN)
        4. Data Output/Data Ready (DOUT/DRDY)
      2. 10.5.2 Data Ready (DRDY)
        1. DRDY in Continuous-Conversion Mode
        2. DRDY in Pulse-Conversion Mode
        3. Data Ready by Software Polling
      3. 10.5.3 Conversion Data
        1. Status Byte (STATUS0)
        2. Conversion Data Format
      4. 10.5.4 Cyclic Redundancy Check (CRC)
      5. 10.5.5 Commands
        1.  General Command Format
        2.  NOP Command
        3.  RESET Command
        4.  START Command
        5.  STOP Command
        6.  RDATA Command
        7.  OFSCAL Command
        8.  GANCAL Command
        9.  RREG Command
        10. WREG Command
        11. LOCK Command
        12. UNLOCK Command
    6. 10.6 Register Map
      1. 10.6.1  Device Identification (ID) Register (address = 00h) [reset = 6xh]
        1. Table 30. ID Register Field Descriptions
      2. 10.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
        1. Table 31. STATUS0 Register Field Descriptions
      3. 10.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 32. MODE0 Register Field Descriptions
      4. 10.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 33. MODE1 Register Field Descriptions
      5. 10.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 34. MODE2 Register Field Descriptions
      6. 10.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 35. MODE3 Register Field Descriptions
      7. 10.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 36. REF Register Field Descriptions
      8. 10.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 10.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 10.6.10 Current Source Multiplexer (I_MUX) Register (address = 0Dh) [reset = FFh]
        1. Table 39. I_MUX Register Field Descriptions
      11. 10.6.11 Current Source Magnitude (I_MAG) Register (address = 0Eh) [reset = 00h]
        1. Table 40. I_MAG Register Field Descriptions
      12. 10.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 41. RESERVED Register Field Descriptions
      13. 10.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
        1. Table 42. MODE4 Register Field Descriptions
      14. 10.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
        1. Table 43. STATUS1 Register Field Descriptions
      15. 10.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
        1. Table 44. STATUS2 Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Input Range
      2. 11.1.2 Input Overload
        1. Input Signal Rate of Change (dV/dt)
      3. 11.1.3 Unused Inputs and Outputs
    2. 11.2 Typical Applications
      1. 11.2.1 ±10-V Analog Input Module
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 11.2.2 Thermocouple Input With High Common-Mode Voltage
    3. 11.3 Initialization Setup
  12. 12Power Supply Recommendations
    1. 12.1 Power-Supply Decoupling
    2. 12.2 Analog Power-Supply Clamp
    3. 12.3 Power-Supply Sequencing
    4. 12.4 5-V to ±15-V DC-DC Converter
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報




The ADS125H02 is a ±20-V signal input, 24-bit, 40-kSPS, delta-sigma (ΔΣ) analog-to-digital converter. The device features gain from 0.125 to 128 that program the input voltage range from ±20 V to ±20 mV (VREF = 2.5 V). The inputs are configurable as one differential input or two single-ended inputs. The device includes a low-noise, low-drift PGA with high input impedance, signal monitors to detect overload conditions, and a voltage reference. A temperature sensor is provided to monitor the surrounding temperature.

The ADC provides a compact one-chip measurement solution for a wide range of input voltages, including typical current and voltage inputs to industrial programmable logic controllers (PLCs), such as ±10-V and 4-mA to 20-mA transmitters (using an external shunt resistor). The ADC provides the resolution necessary to interface directly to low-level sensors such as strain-gauge sensors, thermocouples, and resistance temperature detectors (RTDs). Four general-purpose, input/output (GPIO) pins expand the number of measurement channels with the use of an external multiplexer. Two current sources (IDAC1 and IDAC2) are provided for RTD biasing.

In summary, the ADC features:

  • 12 selectable gains for input ranges from ±20 mV to ±20 V (differential)
  • 1-GΩ input impedance PGA
  • 2.5-V voltage reference
  • Internal or external reference operation
  • Internal or external clock operation
  • PGA, voltage reference, and power-supply monitors
  • Temperature sensor
  • SPI-compatible serial interface with CRC error check
  • Two IDACs
  • Four GPIOs

Analog inputs (AIN0, AIN1, AINCOM) connect to the input multiplexer (MUX) to select the ADC input channel. The ADC supports one differential or two single-ended input measurement configurations.

The programmable gain amplifier (PGA) follows the input multiplexer. The PGA is a high input impedance, complementary metal oxide semiconductor (CMOS), differential-input and differential-output amplifier. The PGA has gain and attenuation modes to match the signal amplitude requirements. In attenuation mode, the PGA reduces the input voltage to the range of the ADC. In gain mode, the input voltage is amplified to the range of the ADC. The PGA output connects to the CAPP and CAPN pins. The ADC antialias filter is provided by the combination of the internal PGA output resistors and the external capacitor connected to these pins.

The input channel multiplexer and the PGA are powered by the high-voltage power-supply pins (HV_AVDD and HV_AVSS).

The operating state of the PGA are monitored for signal out-of-range conditions. Status bits in the status register indicate the possible PGA out-of-range conditions.

The ΔΣ modulator measures the input voltage relative to the reference voltage to produce a 24-bit conversion result. The input range of the ADC is ±VREF / Gain, where gain is programable in binary steps from 0.125 to 128.

The ADC reference voltage is either internal (2.5 V) or external. The REFOUT pin is the internal reference voltage output (with respect to the AGND pin). The reference is monitored for out-of-range conditions and the status is reflected in the conversion data STATUS byte. The device provides two pairs of voltage reference input pins (REFP0, REFN0 and REFP1, REFN1).

The digital filter both averages and reduces the data rate of the modulator output to provide the output conversion result. The sinc filter mode of the digital filter provides programmable orders (sinc1 through sinc5) that allow optimization of conversion latency, conversion noise, and line-cycle rejection. The finite impulse response (FIR) filter mode provides no-latency conversion data with simultaneous rejection of 50-Hz and 60-Hz interference for data rates of 20 SPS or less.

User-programmable offset and gain calibration registers correct the conversion data to provide the final conversion result.

The SPI-compatible serial interface is used to read the conversion data and for ADC configuration and control. Integrity of SPI I/O communication is validated by CRC error checking. The serial interface consists of the following signals: CS1, CS2, SCLK, DIN, and DOUT/DRDY (see the Chip-Select Pins (CS1 and CS2) section for details). The dual-function DOUT/DRDY pin combines the functions of the serial data output and data-ready indication into one pin. DRDY is the data-ready output signal.

The device includes two current sources (IDAC1, IDAC2). The IDACs are powered by the 5-V AVDD power supply. The IDACs provide excitation current to RTDs or other sensors that require constant-current excitation.

The device provides four GPIO pins to control an external signal multiplexer and for general-purpose I/O of 0-V to 5-V logic signals.

The ADC has an internal temperature sensor to monitor the surrounding temperature. The high-voltage power supply is available for readback by the ADC for user diagnostics.

Clock operation is either controlled by the internal oscillator or by an external clock source. The external clock is automatically detected by the ADC. The nominal clock frequency is 7.3728 MHz (10.24 MHz for data rates equal to 40 kSPS).

ADC conversions are controlled by the START pin or by the START command. Conversions are programmable for either continuous mode (gated by START) or one-shot (pulse) conversions.

The ADC auto-resets at power-on, or is manually reset by the RESET input or by the RESET command.

The HV_AVDD and HV_AVSS power supplies allow either bipolar or unipolar configuration (bipolar: ±5 V to ±18 V, unipolar: 10 V to 36 V). The digital I/Os are powered by DVDD (3-V to 5-V range). An internal 2-V subregulator powers the ADC digital core for the DVDD supply. An external bypass capacitor is required at the subregulator output (BYPASS pin).