JAJSGG2C October 2018 – June 2019 ADS125H02
The PGA is a low-noise, programmable gain and attenuation, CMOS differential-input, differential-output amplifier. The PGA operates in gain or attenuation mode depending on the gain selected. Typically, the PGA is programmed to provide gain when the expected range of the input signal is less than the reference voltage and is programmed to provide attenuation when the expected range of the input signal is greater than the reference voltage.
Figure 57 shows the block diagram of the PGA.
The PGA inputs are filtered by an RC network to decrease sensitivity to radio frequency interference (RFI) and electromagnetic interference (EMI) interference. The PGA is comprised of two stages: a gain stage followed by an attenuation stage. The first stage is a high input impedance, noninverting differential amplifier (amplifiers A1 and A2) and provides the PGA gain.
The second stage is an inverting, differential amplifier (amplifiers A3 and A4) and provides the attenuation stage. The second stage provides the PGA attenuation for high-amplitude signals. The common-mode voltage of the differential signal is shifted to AVDD / 2. The second stage drives the modulator input of the ADC and is also connected to the CAPP and CAPN pins. An external 1-nF capacitor filters the modulator input sampling pulses and also provides the antialias filter. Place the capacitor close to the pins using short, direct traces. Avoid running clock traces or other digital traces underneath or in the vicinity of these pins.
Amplifiers A1 and A2 have inverse-parallel-connected protection diodes across the amplifiers inputs to clamp the voltage under signal overrange conditions. When the input is overranged, the diodes may conduct resulting in current flow through the diodes, and subsequently, through the analog input pins. Conditions of high dV/dt input signals, such as those generated by the switching of a signal multiplexer, can lead to transient turn-on of the clamp diodes. Use an RC filter at the PGA inputs to limit the dV/dt of the signal to reduce turn-on of the clamp diodes.
The PGA is monitored for high and low operating voltage headroom at four signal points. The output of the eight total monitor outputs are ORed together into a single error bit contained in the conversion data status byte and the STATUS0 register.