JAJSGG2C October 2018 – June 2019 ADS125H02
As with many amplifiers, the PGA limits the absolute input voltage that must not be exceeded in the linear operating range. The absolute voltage is the combined differential and common-mode voltages. The maximum allowable absolute voltage is determined by the PGA gain, the maximum differential input voltage (VIN), and the minimum value of the high-voltage power supply. Maintain the absolute input voltage (VAINX) within the range as shown in Equation 5, otherwise incorrect conversion data can result:
The differential input signal can also be limited by two other conditions. The first limiting condition is when the reference voltage exceeds AVDD – 1 V (nominally VREF > 4 V). In this case, the differential input signal is limited to: VIN = ±(AVDD – 1 V) / Gain, instead of the ideal VIN = ±VREF / Gain. The second limiting condition applies to gains of 0.125 and 0.1875. In this case, the differential input signal is limited to: VIN = ±20 V, regardless of the reference voltage.
Figure 58 and Figure 59 show the relationship between the PGA input voltage to the PGA output voltage. In attenuation mode, the first PGA stage is configured as a unity-gain follower. The second PGA stage attenuates the differential input and shifts the signal common-mode voltage to AVDD / 2 to drive the ADC input.
In gain mode, the first PGA stage amplifies the differential signal. The second PGA stage is configured as a unity-gain follower with level-shift. Figure 58 and Figure 59 show the corresponding output voltage of the PGA stages that must have operating voltage headroom.