JAJSGG2C October 2018 – June 2019 ADS125H02
The PGA requires operating voltage headroom at the input and output nodes. The PGA must be within the linear operating range, otherwise the conversion data are not valid. Use the internal PGA monitors to assist in the detection of PGA overload. The PGA has four monitors (two monitors for the input and two monitors for the output) with high and low thresholds for each, for a total of eight possible alarms. The status of each PGA monitor is read in the STATUS1 register. The PGA monitoring points are illustrated in Figure 57. Figure 60 shows the operation of the low-overload threshold and the high-overload threshold of each PGA monitor point.
Check for PGA overload by polling the STAT12 bit (bit 4 of the STATUS conversion byte or STATUS0 register). The STAT12 bit is the logical OR of all PGA error flags with the CRC-2 error flag. After the STAT12 bit asserts, poll the STATUS1 and STATUS2 registers (address 11h and 12h) to determine the source of the error. The status of the PGA overload is latched in the STATUS1 register and remains latched after the overload condition is removed. Reading the STATUS1 register clears the PGA overload bits (clear-on-read operation). The PGA overload flags and the CRC2 flag must be reset in order to clear the STAT12 bit. See the STATUS1 register for a description of the PGA overload bits.
The PGA monitors are analog comparators that can respond to transient overload conditions. Transient conditions can occur, for example, when multiplexing the inputs or when the gain is too high for the voltage of the next channel.