JAJSGG2C October 2018 – June 2019 ADS125H02
The sinc filter consists of two stages: a variable-decimation sinc5 filter followed by a variable-decimation, variable-order sinc filter. The first stage sinc5 filter averages and down-samples the modulator data (fCLK / 8) to produce 40000 SPS, 25600 SPS, 19200 SPS, and 14400 SPS by using decimation ratios of 32, 36, 48, and 64, respectively. These data outputs bypass the second filter stage and as a result have response characteristics of the first-stage sinc5 filter. The second stage receives the first stage output data at 14400 SPS, and performs additional filtering and decimation to yield data rates of 7200 SPS to 2.5 SPS. The second stage is a programmable order sinc filter.
The data rate is programmed by the DR[4:0] bits of the register MODE0. The filter mode is programmed by the FILTER[2:0] bits of the MODE0 register.