JAJSGG2C October 2018 – June 2019 ADS125H02
The digital filter averages data from the modulator to produce the conversion result. The discrete stages of the digital filter must have settled data to provide fully settled output data. The order and the decimation ratio of the digital filter determine the amount of data averaged that affects the latency of the conversion data. The FIR and sinc1 filter modes are zero latency because the ADC provides the conversion result in one conversion cycle. Latency time is an important consideration for data throughput in multiplexed applications.
Table 8 lists the conversion latency values of the ADC. Conversion latency is defined as the time from the start of the first conversion by taking the START pin high or sending the start command to when the conversion data are ready. The ADC is designed to provide fully settled data under this condition. The conversion latency values listed in Table 8 include the programmable start-conversion delay equal to 50 µs before the digital filter starts, which also includes overhead time for final data processing. After the first conversion completes in continuous conversion mode, the period of the next conversions are equal to 1 / fDATA. The first conversion latency time in auto-zero mode has twice the values listed in Table 8. The values listed in Table 8 are equal to the period of the next conversions.
|CONVERSION LATENCY TIME (t(STDR)(1), ms)|
As shown in Figure 77, if the input signal changes during the conversion phase, the conversion data are a mix of old and new data. After an unsynchronized input change, the number of conversion periods required to provide fully settled output data are calculated by dividing the conversion latency by the nominal period and then adding one additional conversion. In auto-zero mode, use twice the latency values plus one additional conversion.