JAJSGG2C October 2018 – June 2019 ADS125H02
After supply voltages cross the respective reset voltage thresholds at power-up, the ADC is reset and after 216 fCLK cycles the ADC is ready for communication. Until this time, DRDY is held low. DRDY is then driven high to indicate when ADC communication can begin. The conversion cycle starts 512 / fCLK cycle after DRDY asserts high. Figure 4 illustrates the power-on reset behavior.