JAJSGG2C October 2018 – June 2019 ADS125H02
The ADC consists of discrete PGA and ADC sections with each section selected for communication by separate chip-select inputs (CS1 and CS2). Most commands require the use of CS1 to control the ADC section. However, for control of the PGA section, use CS2 for register access commands at address 10h and above. Communicate to the device by taking either CS1 or CS2 low corresponding to the type of command and whether addressing the ADC or PGA registers.
CS1 and CS2 are active low inputs. In normal operation, take one chip-select input low at a time and keep that input low for the duration the command operation. Take the chip-select input high after the command operation completes. When the chip-select input is taken high, the serial interface resets and SCLK activity is ignored (thus blocking commands). When both chip-select inputs are high, DOUT/DRDY enters the high-impedance state. CS1 must be low in order to poll the data-ready function provided by DOUT/DRDY. DRDY remains active regardless of the state of the chip-select inputs.