JAJSGG2C October 2018 – June 2019 ADS125H02
SCLK is the serial interface shift clock input that clocks data into and out of the device. Output data are updated on the rising edge of SCLK and input data are latched on the falling edge of SCLK. Return SCLK low after the data operation completes. SCLK is a Schmidt-triggered input designed to provide noise immunity. Even though SCLK is noise resistant, keep SCLK noise-free as possible to avoid unintentional SCLK transitions. Avoid ringing and overshoot on the SCLK input. Use a series termination resistor at the SCLK drive pin to reduce ringing.