JAJSGG2C October 2018 – June 2019 ADS125H02
Cyclic redundancy check (CRC) is an error detection byte that detects communication errors to and from the host and ADC. CRC is the division remainder of the payload data by the prescribed CRC polynomial. The payload data are 1, 2, 3, or 4 bytes depending on the data transfer operation.
The host computes the CRC over the two command bytes and appends the CRC to the command string (third byte). A fourth, zero-value byte completes the command field to the ADC. The ADC performs the CRC calculation and compares the result to the CRC transmitted by the host. If the host and ADC CRC values match, the command executes and the ADC responds by transmitting the valid CRC during the fourth byte of the command. If the CRC is error free and the operation is a data read, the ADC responds with a second CRC that is computed for the requested data byte payload. The response data payload is 1, 3, or 4 bytes depending on the type of operation.
If the host and ADC CRC values do not match, the command does not execute and the ADC responds with an inverted CRC value, calculated over the received command bytes. The inverted CRC is intended to signal the host of the failed operation. The host terminates transmission of further bytes to stop the command operation. The CRC1 bit is set in the STATUS0 register when a error pertaining to ADC registers occur. The STAT12 and CRC2 flags are set when an error pertaining to PGA registers occur.
The ADC is ready to accept the next command after all required bytes are transmitted when no CRC error occurs, or after a CRC error occurs when terminated at the end of the fourth command byte.
The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) of the argument by a CRC polynomial. The CRC polynomial is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X + 1. The nine binary polynomial coefficients are: 100000111b.
The following is a general procedure to compute the CRC value: