JAJSGG2C October 2018 – June 2019 ADS125H02
Figure 80 shows an example register write operation to register address 02h (command opcode 42h). For this register address (02h), take CS1 low. The first byte output from the ADC is always 0FFh. The host calculates the CRC of the two input command bytes. The Out CRC-2 byte is the ADC-calculated, output CRC based on the received command bytes. If the CRC values match, the command is executed beginning at the last SCLK of the fourth byte in the sequence. Forcing chip select high before the command completes results in command termination. Toggle chip select low-to-high between command operations.
The following sections detail the input and output byte sequence corresponding to each command. See the Cyclic Redundancy Check (CRC) section for the notation used for the CRC.