JAJSIU8B June 2015 – April 2020 ADS131E08S
The digital filter receives the modulator output bit stream and decimates the data stream. The decimation ratio determines the number of samples taken to create the output data word, and is set by the modulator rate divided by the data rate (fMOD / fDR). By adjusting the decimation ratio, a tradeoff can be made between resolution and data rate: higher decimation allows for higher resolution (thus creating lower data rates) and lower decimation decreases resolution but enables wider bandwidths with higher data rates. Higher data rates are typically used in power applications that implement software re-sampling techniques to help with channel-to-channel phase adjustment for voltage and current.
The digital filter on each channel consists of a third-order sinc filter. An input step change takes three conversion cycles for the filter to settle. Adjust the decimation ratio of the sinc3 filters using the DR[2:0] bits in the CONFIG1 register (see the Register Map section for details). The data rate setting is a global setting that sets all channels to the same data rate.
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. The sinc3 filter attenuates the high-frequency modulator noise, then decimates the data stream into parallel data. The decimation rate affects the overall converter data rate.
Equation 5 shows the scaled sinc3 filter Z-domain transfer function.
The sinc3 filter frequency domain transfer function is shown in Equation 6.
The sinc3 filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 24 illustrates the sinc filter frequency response and Figure 25 illustrates the sinc filter roll-off. Figure 26 and Figure 27 illustrate the filter transfer function until fMOD / 2 and fMOD / 16, respectively, at different data rates. Figure 28 illustrates the transfer function extended until 4 fMOD. Figure 28 illustrates that the ADS131E08S passband repeats itself at every fMOD. Note that the digital filter response and filter notches are proportional to the master clock frequency.