JAJSIU8B June 2015 – April 2020 ADS131E08S
When the device is converting and there is a step change on the input signal, a delay of 3 tDR is required for the output data to settle. Settled data are available on the fourth DRDY pulse. Data are available to read at each DRDY low transition prior to the 4th DRDY pulse, but are recommended to be ignored. Figure 33 shows the required wait time for complete settling for an input step or input transient event on the analog input.