JAJSIU8B June 2015 – April 2020 ADS131E08S
The ADS131E08S serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute each command. This timing requirement can place restrictions on the SCLK speed and operational modes. For example:
Assuming CLK is 2.048 MHz, then tSDECODE (4 tCLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be transferred in 0.5 µs. This byte transfer time does not meet the tSDECODE specification; therefore, a delay of 1.46 µs (1.96 µs – 0.5 µs) must be inserted after the first byte and before the second byte. If SCLK is 4 MHz, one byte is transferred in 2 µs. Because this transfer time exceeds the tSDECODE specification (2 µs > 1.96 µs), the processor can send subsequent bytes without delay.