JAJSIU8B June 2015 – April 2020 ADS131E08S
Settled data from the ADS131E08S are available within 3 ms of power-up if a strict timing sequence is followed. Before device power-up, all digital and analog inputs must be held low. Provide the master clock 50 µs after the analog and digital supplies reach 90% of their nominal values, shown as tPCLK in Figure 66. Pull the RESET pin high following the tPRST timing to bring the ADC digital filters out of a reset state and to begin the conversion process.
Settled data are available at the first DRDY falling edge, shown as tSETTLE in Figure 66. These data are from the settled digital filter; however, the first data set may not be a settled representation of the input because additional time is required for the reference and critical voltage nodes to settle to their final values. The tSTABLE timing adds the recommended wait time for settled data to be available at the ADC output. When the tSTABLE time has passed, the next DRDY falling edge indicates a valid conversion result of the input signal where both the digital filter and node voltages are settled.
|tPCLK||Delay time, first external CLK rising edge after AVDD reaches 90%||50||µs|
|Delay time, internal oscillator start-up after AVDD reaches 90%||20|
|tPRST||Delay time, RESET rising edge after first CLK rising edge||2||tCLK|
|tSETTLE||Settling time, first settled data after RESET rising edge(1)||2312||tCLK|
|tSTABLE||Settling time, valid data after RESET rising edge||2.2||ms|
To deviate from the default register settings, write to the ADS131E08S registers after pulling the RESET pin high. Changes to any of the registers delay the tSETTLE start point until the register write is complete. If the data rate is changed following the RESET pin going high, the tSETTLE timing takes on the settling characteristics of Table 5 relative to the completion of the command.