7.3.1 Analog Inputs

The ADS58J63 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source which enables great flexibility in the external analog filter design as well as excellent 50 Ω matching for RF applications. The buffer also helps to isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.475 V) and (VCM – 0.475 V), resulting in a 1.9-Vpp (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 900 MHz.

7.3.2 Recommended Input Circuitry

In order to achieve optimum AC performance the following circuitry is recommended at the analog inputs.

Figure 51. Analog Input Driving Circuit

7.4.1 Digital Features

The ADS58J63 supports decimation by 2 and 4 and burst mode output. The 4 channels can be configured as pairs (A and B and C and D) to either burst or decimation mode (must be same decimation mode for all 4 channels).

Figure 52 shows signal processing in Digital Down-Conversion (DDC) Block in ADS58J63.

Figure 52. Digital Down-Conversion (DDC) Block

Table 2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.

7.4.2 Mode 0 – Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

In this configuration, the DDC block includes a fixed frequency ±Fs/4 complex digital mixer preceding the digital filter – so the IQ passband is ± ~110 MHz (3 dB) centered at Fs/4. Mixing with +FS/4 inverts the spectrum. The stop band attenuation is approximately 90 dB and the passband flatness is ±0.1 dB. Figure 53 shows mixing operation in DDC Mode 0.

Figure 53. Mixing in Mode 0

Figure 54. Frequency Response of Filter in Mode 0

Figure 55. Zoomed view of Frequency Response

7.4.3 Mode 2 – Decimation by 2 for up to 110 MHz of Real Bandwidth

In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs. The passband is ~110 MHz (3 dB). Figure 56 shows filtering operation in DDC Mode 2.

Figure 56. Filtering in Mode 2

Figure 57. Frequency Response for Decimate-by-2 Low Pass and High Pass Filter (in Mode 2)

Figure 58. Zoomed View of Frequency Response

7.4.4 Mode 4/7 – Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth

In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7) preceding the decimation by 2 digital filter also with an IQ passband of ± ~55 MHz (3 dB) centered at N×Fs/16. A positive value for N inverts the spectrum. In addition a Fs/8 complex digital mixer is added after the decimation filter transforming the output back to real format while centering the output spectrum within the Nyquist zone.

In addition the ADS58J63 supports a 0-pad feature where a sample with value = 0 gets added after each sample. In that way the output data rate gets interpolated to 500 Msps (real) with a 2^nd image inverted at Fs/2-Fin.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for out of band aliases. The passband flatness is ±0.1 dB.

Figure 59. Mixing and Filtering in Mode 4/7

Figure 60. Frequency Response for Decimate-by-2 Low-Pass Filter (in Mode 4 and Mode 7)

Figure 61. Zoomed View of Frequency Response

7.4.5 Mode 5 – Decimation by 2 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7) preceding the decimation by 2 digital filter – so the IQ passband is ± ~55 MHz (3 dB) centered at N×Fs/16. A positive value for N inverts the spectrum.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The passband flatness is ±0.1 dB.

Figure 62. Mixing and Filtering in Mode 5

Figure 63. Frequency Response for Decimate-by-2 Low-Pass Filter (in Mode 5)

Figure 64. Zoomed View of Frequency Response

7.4.6 Mode 6 – Decimation by 4 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable n×Fs/16 complex digital mixer (n from –8 to +7) preceding the decimation by 4 digital filter – so the IQ passband is ± ~55 MHz (3 dB) centered at n×Fs/16. A positive value for N inverts the spectrum. The decimaiton by 4 filter is a cascade of two decimation by 2 filters with frequency response shown in Figure 66.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for out of band aliases. The passband flatness is ±0.1 dB.

Figure 65. Mixing and Filtering in Mode 6

Figure 66. Frequency Response for Decimate-by-2 Low-Pass Filter (in Mode 6)

Figure 67. Zoomed View of Frequency Response

7.4.7 Mode 8 – Burst Mode

In burst mode the output data is alternated between low resolution (L, 9-bit) and high resolution (H, 14-bit) output. The burst mode can be configured via SPI register writes independently for channel A/B and channel C/D.

The high resolution output is 14 bit and the number (#) of high and low resolution samples is set with two user programmable counters – one for high resolution (HC) and one for low resolution (LC). There is one counter pair (HC, LC) for channel A/B and one pair for channel C/D. The internal logic checks if the maximum duty cycle is exceeded and if necessary resets the counters to its default values.

Each output cycle starts with a low resolution and the counter values can be reconfigured for the next cycle during prior to the start of the next cycle.

Figure 68. Timing Diagram for 14-bit Burst Mode (DDC Mode 8)

The counter values for high and low resolution can be programmed to:

High resolution counter (HC): 1 to 2²⁵

Low resolution counter (LC); 1 to 2²⁸

The output duty cycle limit is illustrated in Table 8.

7.4.8 Trigger Input

The burst mode can be operated in auto trigger or manual trigger mode. In manual trigger mode the TRIGGER input (TRIGAB, TRIGCD) is used to release the high resolution data (HC) burst after the low resolution data counter LC has timed out. In auto trigger mode the high resolution data is released immediately after completion of the last low resolution sample.

Using SPI control the ADS58J63 can be configured to use TRIGAB or TRIGCD as the manual trigger input.

7.4.9 Manual Trigger Mode

Upon enabling manual trigger mode, the ADS58J63 starts transmission of low resolution data. As soon as the LC counter is finished, the manual trigger is unlocked, the trigger ready flag (TRDY) is raised and the high resolution output H can be triggered. Once the low resolution counter LC is finished, the next high resolution output or burst mode sequence can be triggered again. The HRES flag is embedded in the JESD204B output data stream. The counter values can be updated until a new burst mode cycles starts with transmission of low resolution samples.

Example of burst mode with manual trigger:

Figure 69. Timing Diagram for Manual Trigger Mode

7.4.10 Auto Trigger Mode

Upon enabling auto trigger mode, the ADS58J63 starts transmission of low resolution data. As soon as the low resolution samples counter (LC) is finished, the ADS58J63 immediately begins transmitting the high resolution output H. The HRES flag can also be embedded in the JESD204B output data stream. The counter values can be updated until a new burst mode cycles starts with transmission of low resolution samples. Any input on the trigger input pins is ignored.

Example of burst mode with automatic trigger:

Figure 70. Timing Diagram for Auto Trigger Mode

7.4.11 Over-range Indication

The ADS58J63 provides a fast over-range indication (FOVR) which can be presented in the digital output data stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the LSB (normal 0) of the 16 bit going to the 8b/10b encoder.

One threshold is set per channel pair A/B and C/D.

Figure 71. Timing Diagram for FOVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.

The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using the FOVR THRESHOLD bits.

The input voltage level at which fast OVR is triggered is:
Full-scale × [the decimal value of the FOVR Threshold bits] / 255)
The default threshold is E3h (227) which corresponds to a threshold of –1 dBFS.

In terms of full scale input, the fast OVR threshold can be calculated as shown in Equation 1:

Following is an example register write to set the FOVR threshold for all 4 channels:

7.4.12 Power-Down Mode

The ADS58J63 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN pin or SPI register writes.

A power-down mask can be configured, which allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2 as shown in Table 10. See the master page registers in Table 15 for further details.

To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However, when JESD link must remain up while putting the device in power down, the ADC and analog buffer can be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 11 shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits.

7.5.1 Device Configuration

The ADS58J63 can be configured using a serial programming interface, as described below. In addition, the device has one dedicated parallel pin (PDN) for controlling the power down modes. The ADS58J63 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see detailed register map info) to access all register bits.

7.5.1.1 Details of Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can work with SCLK frequencies from 5 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty cycle.

Figure 72. Serial Interface Timing Diagram

Table 12. Programing Details of Serial Interface

SPI BITS	DESCRIPTION	OPTIONS
R/W	Read/write bit	0 = SPI write 1 = SPI read back
M	SPI bank access	0 = Analog SPI bank (Master and ADC page) 1 = JDigital SPI bank (Main Digital, Analog JESD, and Digital JESD pages)
P	JESD page selection bit	0 = Page access 1 = Register access
CH	SPI access for a specific channel of the digital SPI bank	0 = Channel AB 1 = Channel CD By default, both channels are being addressed.
ADDR [11:0]	SPI address bits	—
DATA [7:0]	SPI data bits	—

7.5.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS58J63 analog SPI bank can be programmed by:

1. Drive the SEN pin low.
2. Initiate a serial interface cycle specifying the page address of the register whose content must be written.
   • Master page: write address 0011h with 80h.
   • ADC page: write address 0011h with 0Fh.
3. Write the register content as shown in Figure 73. When a page is selected, multiple writes into the same page can be done.

Figure 73. Serial Register Write Timing Diagram

7.5.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

1. Drive the SEN pin low.
2. Select the page address of the register whose content must be read.
   • Master page: write address 0011h with 80h.
   • ADC page: write address 0011h with 0Fh.
3. Set the R/W bit to 1 and write the address to be read back.
4. Read back the register content on the SDOUT pin, as shown in Figure 74. When a page is selected, multiple read backs from the same page can be done.

Figure 74. Serial Register Read Timing Diagram

7.5.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains four pages (main digital, interleaving engine, digital, and analog JESD pages). The individual pages can be selected by:

1. Drive the SEN pin low.
2. Set the M bit to 1 and specify the page with two register writes. Note that the P bit must be set to 0, as shown in Figure 75.
   • Write address 4003h with 00h (LSB byte of page address).
   • Write address 4004h with the MSB byte of the page address.
     • For Main digital page: write address 4004h with 68h.
     • For Digital JESD page: write address 4004h with 69h.
     • For Analog JESD page: write address 4004h with 6Ah.
     • For Interleaving engine page: write address 4004h with 61h.

Figure 75. SPI Page Selection

7.5.1.5 Serial Register Write: Analog Bank

The analog SPI bank contains two pages (Master and ADC page). The internal register of the ADS58J63 analog SPI bank can be programmed following these steps:

1. Drive the SEN pin low.
2. Initiate a serial interface cycle specifying the page address of the register whose content has to be written
   • Master page: write address 11h with 80h
   • ADC page: write address 11h with 0Fh
3. Write register content. Once a page is selected, multiple writes into the same page can be done.

Figure 76. Serial Register Write Timing Diagram

7.5.1.6 Serial Register Readout: Analog Bank

SPI read out of content in one of the two analog banks can be accomplished with the following steps:

1. Drive the SEN pin low.
2. Select the page address of the register which content has to be read.
   • Master page: write Address = 11h with 80h
   • ADC page: write Address 11h with 0Fh.
3. Set the R/W bit to '1' and write the address to be read back.
4. Read back register content on the SDOUT pin. Once a page is selected, multiple read backs from the same page can be done.

Figure 77. Serial Register Read Timing Diagram

7.5.1.7 Digital Bank SPI Page Selection

The Digital SPI bank contains five pages (Main digital, Interleaving Engine, Decimation filter, JESD digital, and JESD analog). The individual pages can be selected following these steps:

1. Drive the SEN pin low.
2. Set the M bit to ‘1’ and specify the page with two register writes (Note: P bit set to 0)
   • Write address 4003h with 00h (LSB byte of page address)
   • Write address 4004h MSB byte of page address

   spacer

   • Main digital page: write Address = 4004h with 68h (default)
   • Digital JESD page: write Address = 4004h with 69h
   • Analog JESD page: write Address = 4004h with 6Ah
   • Interleaving Engine page: write Address = 4004h with 61h
   • Decimation Filter page: write Address = 4004h with 61h and 4003h with 41h

Figure 78. SPI Timing Diagram for Digital Bank Page Selection

7.5.1.8 Serial Register Write – Digital Bank

The ADS58J63 is a quad channel device and the JESD204B portion is configured individually for 2 channel (A/B and C/D) using the CH bit. Note the P bit needs to be set to 1 for register writes.

1. Drive the SEN pin low.
2. Select the digital bank page (Note: M bit = 1, P bit = 0)
   • Write address 4003h with 00h
   • Main digital page: write Address = 4004h with 68h (default)
   • Digital JESD page: write Address = 4004h with 69h
   • Analog JESD page: write Address = 4004h with 6Ah
   • Interleaving Engine page: write Address = 4004h with 61h
   • Decimation Filter page: write Address = 4004h with 61h and 4003h with 41h
3. Set M and P bit to 1 and select ChAB (CH=0) or ChCD (CH=1) and write register content. Once a page is selected, multiple writes into the same page can be done.
   By default, register writes are applied to both channel pairs (broadcast mode). To disable broadcast mode and enable individual channel writes, write address 4005h with 01h (default is 00h).

Figure 79. Serial Register Write Timing Diagram

Figure 80. Serial Register Read Timing Diagram

7.5.2 JESD204B Interface

The ADS58J63 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. The ADS58J63 supports single (for all 4 JESD links) or dual (for channel A/B and C/D) SYNCb inputs and can be configured via SPI.

Figure 81. JESD Interface Block Diagram

Depending on the ADC sampling rate, the JESD204B output interface can be operated with 1 lane per channel. The JESD204B setup and configuration of the frame assembly parameters is handled via SPI interface.

The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally data from the transport layer can be scrambled.

Figure 82. JESD204B Transmitter Block

7.5.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon detecting a logic low on the SYNC input pins, the ADS58J63 starts transmitting comma (K28.5) characters to establish code group synchronization.

Once synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS58J63 starts the initial lane alignment sequence with the next local multi frame clock boundary. The ADS58J63 transmits 4 multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the 2^nd multi-frame also contains the JESD204 link configuration data.

Figure 83. ILA Sequence

7.5.2.3 JESD Output Switch

The ADS58J63 provides a digital cross point switch in the JESD204B block which allows internal routing of any output of the 2 ADCs within one channel pair to any of the 2 JESD204B serial transmitters in order to ease layout constraints. The cross point switch routing is configured via SPI (address 21h in JESD digital page).

Figure 84. Switching the Output Lanes

7.5.2.3.1 Serdes Transmitter Interface

Each of the 10 Gbps serdes transmitter outputs requires AC coupling between transmitter and receiver. The differential pair should be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted reflections and signal degradation.

Figure 85. Serdes Transmitter Connection to Receiver

7.5.2.3.2 SYNCb Interface

The ADS58J63 supports single (either SYNCb input controls all 4 JESD204B links) or dual (1 SYNCb input controls 2 JESD204B lanes (DA/DB and DC/DD) SYNCb control. When using single SYNCb control, the unused input should be connected to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).

7.5.2.3.3 Eye Diagram

Figure 86 to Figure 89 show the serial output eye diagrams of the ADS58J63 at 5 Gbps and 10 Gbps with default and increased output voltage swing against the JESD204B mask.

Figure 86. Eye at 5-Gbps Bit Rate with
Default Output Swing

Figure 88. Eye at 10-Gbps Bit Rate with
Default Output Swing

Figure 87. Eye at 5-Gbps Bit Rate with
Increased Output Swing

Figure 89. Eye at 10-Gbps Bit Rate with
Increased Output Swing

7.6.1 Detailed Register Info

The ADS58J63 contains two main SPI banks. The analog SPI bank gives access to the ADC cores while the digital SPI bank controls the serial interface. The analog SPI bank is divided into two pages (MASTER and ADC) while the digital SPI bank is divided into five pages (Main digital, Interleaving Engine, Decimation filter, JESD digital, and JESD analog).

7.6.2 Example Register Writes

Global Power Down

Change decimation mode 0 (default) to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as well as serial output data rate (10 Gbps to 5 Gbps).

7.6.3 Register Descriptions