SBAS608C June 2014 – December 2015 ADS7042
PRODUCTION DATA.
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NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The two primary circuits required to maximize the performance of a highprecision, successive approximation register (SAR), analogtodigital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides some application circuits designed for the ADS7042.
The goal of this application is to design a singlesupply digital acquisition (DAQ) circuit based on the ADS7042 with SNR greater than 68 dB and THD less than –80 dB for input frequencies of 2.5 kHz at a throughput of
1 MSPS.
The input driver circuit for a highprecision ADC mainly consists of two parts: a driving amplifier and an antialiasing filter. Careful design of the frontend circuit is critical to meet the linearity and noise performance of a highprecision ADC.
Converting analogtodigital signals requires sampling an input signal at a rate greater than or equal to the Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and folded back into the lowfrequency spectrum. This process is called aliasing. Therefore, an external, antialiasing filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a lowpass RC filter, for which the 3dB bandwidth is optimized for noise, response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a highbandwidth filter is designed to allow accurately settling the signal at the ADC inputs during the small acquisition time window. Figure 39 provides the equation for determining the bandwidth of the antialiasing filter.
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby increasing the signaltonoise ratio (SNR) of the system. Besides filtering the noise from the frontend drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switchedcapacitor input stage of the ADC. A filter capacitor, C_{FLT}, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sampleandhold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
15 pF. Thus, the value of C_{FLT} is greater than 300 pF. Select a COG or NPOtype capacitor because these capacitor types have a highQ, lowtemperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_{FLT}) are used at the output of the amplifiers. A higher value of R_{FLT} is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of R_{FLT} requires balancing the stability and distortion of the design.
The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with highbandwidth amplifiers, some amplifiers can require more bandwidth than others to drive similar filters.
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:
where
where
The OPA314 is selected for this application for its railtorail input and output swing, lownoise (14 nV/√Hz), and lowpower (150 µA) performance to support a singlesupply data acquisition circuit.
The goal of this application is to design a data acquisition circuit based on the ADS7042 with SINAD greater than 69.5 dB for input frequencies up to 250 kHz.
To achieve a SINAD of 69.5 dB, the operational amplifier must have high bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the inputreferred noise of the ADC. For the application circuit shown in Figure 41, the OPA835 is selected for its high bandwidth (56 MHz) and low noise (9.3 nV/√Hz).

For a stepbystep design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD168, Three 12Bit Data Acquisition Reference Designs Optimized for Low Power and UltraSmall Form Factor (TIDU390). 
Figure 42 shows the FFT plot for the ADS7042 with a 2kHz input frequency used for the circuit in Figure 41. Figure 43 shows the FFT plot for the ADS7042 with a 250kHz input frequency used for the circuit in Figure 41.
SNR = 70.62 dB  THD = –83.96 dB  SINAD = 70.3 dB 
Number of samples = 32768 
SNR = 70.22 dB  THD = –81.58 dB  SINAD = 69.8 dB 
Number of samples = 32768 
In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a DAQ circuit can be designed without the input driver for the ADC . This type of a use case is of particular interest for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications that fall into this category are lowpower sensor applications (such as temperature, pressure, humidity, gas, and chemical).
For this design example, use the parameters listed in Table 4 as the input parameters.
DESIGN PARAMETER  GOAL VALUE 

Throughput  10 kSPS 
SNR at 100 Hz  70 dB 
THD at 100 Hz  75dB 
SINAD at 100 Hz  69 dB 
ENOB  11 
Power  10 µW 
The ADS7042 can be directly interfaced with sensors at lower throughputs without the need of an amplifier buffer. The analog input source drive must be capable of driving the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the SAR ADC. However, the output impedance of the sensor must be taken into account when interfacing a SAR ADC directly with sensors. Drive the analog input of the SAR ADC with a low impedance source. The input signal requires more acquisition time to settle to the desired accuracy because of the higher output impedance of the sensor. The simplified circuit for a sensor as a voltage source with output impedance (R_{OUT}) is shown in Figure 44.
The acquisition time of a SAR ADC (such as the ADS7042) can be increased by reducing throughput in the following ways:
Table 5 lists the acquisition time for the above two cases for a throughput of 100 kSPS. Clearly, case 2 provides more acquisition time for the input signal to settle.
CASE  SCLK  t_{cycle}  CONVERSION TIME (= 12.5 × t_{SCLK} + t_{SU_CSCK}) 
ACQUISITION TIME (= t_{cycle} – t_{conv}) 

1  1.6 MHz  10 µs  7.8125 µs  2.1875 µs 
2  16 MHz  10 µs  0.78125 µs  9.21875 µs 

For a stepbystep design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD168, Three 12Bit Data Acquisition Reference Designs Optimized for Low Power and UltraSmall Form Factor (TIDU390). 
When the output impedance of the sensor increases, the time required for the input signal to settle increases and the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time for the input signal to settle. Figure 45 provides the results for ENOB achieved from the ADS7042 for case 2 at different throughputs with different input impedances at the device input.
Table 6 shows the results and performance summary for this 12bit, 10kSPS DAQ circuit application.
DESIGN PARAMETER  GOAL VALUE  ACHIEVED RESULT 

Throughput  10 kSPS  10 kSPS 
SNR at 100 Hz  70 dB  70.6 dB 
THD at 100 Hz  75dB  83.5 dB 
SINAD at 100 Hz  69dB  70.4 dB 
ENOB  11  11.4 
Power  10 µW  7 µW 