SBAS608C June 2014 – December 2015 ADS7042
Figure 47 shows a board layout example for the ADS7042. Use a ground plane underneath the device and partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference input signals away from noise sources. In Figure 47, the analog input and reference signals are routed on the top and left side of the device and the digital connections are routed on the bottom and right side of the device.
The power sources to the device must be clean and well-bypassed. Use 1-μF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-impedance paths. The AVDD supply voltage for the ADS7042 also functions as a reference for the device. Place the decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins and connect CREF to the device pins with thick copper tracks, as shown in Figure 47.
The fly-wheel RC filters are placed close to the device. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.