JAJSHX7A September   2010  – September 2019 ADS7947 , ADS7948 , ADS7949

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ADS794x のブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: ADS794x (12-, 10-, 8-Bit)
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS7947 (12-Bit)
    6. 7.6  Electrical Characteristics: ADS7948 (10-Bit)
    7. 7.7  Electrical Characteristics: ADS7949 (8-Bit)
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics: ADS7947, ADS7948, ADS7949
    11. 7.11 Typical Characteristics: ADS7947 (12-Bit)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer and ADC Input
      2. 8.3.2 Reference
      3. 8.3.3 Clock
      4. 8.3.4 ADC Transfer Function
      5. 8.3.5 Power-Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
    5. 8.5 Programming
      1. 8.5.1 16-Clock Frame
      2. 8.5.2 32-Clock Frame
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving an ADC Without a Driving Op Amp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RTE Package
16-Pin WQFN
Top View
ADS7947 ADS7948 ADS7949 po_las708.gif

Pin Functions

PIN NO. PIN NAME FUNCTION DESCRIPTION
1 GND Analog/digital Power supply ground; all analog and digital signals are referred with respect to this pin.
2 AVDD Analog ADC power supply.
3 REF Analog ADC positive reference input; decouple this pin with REFGND.
4 REFGND Analog Reference return; short to analog ground plane.
5 AIN0P Analog input Positive analog input, channel 0.
6 AIN0N Analog input Negative analog input, channel 0. The allowable signal swing on this pin is ±0.2V; this pin can be grounded.
7 AIN1N Analog input Negative analog input, channel 1. The allowable signal swing on this pin is ±0.2V; this pin can be grounded.
8 AIN1P Analog input Positive analog input, channel 1.
9 NC — Not connected internally, TI recommends externally shorting this pin to GND.
10 NC — Not connected internally, TI recommends externally shorting this pin to GND.
11 CH SEL Digital input This pin selects the analog input channel.
Low = channel 0, high = channel 1.
TI recommends changing the channel within a window of one clock; from half a clock after the CS falling edge. This change ensures the settling on the multiplexer output before the sample start.
12 PDEN Digital input This pin enables a power-down feature if this pin is high at the CS rising edge.
13 CS Digital input Chip-select signal; active low.
14 SCLK Digital input Serial SPI clock.
15 SDO Digital output Serial data out.
16 DVDD Digital Digital I/O supply.