The ADS855x contains six low-power, 16-, 14-, or 12-bit, successive approximation register (SAR) based analog-to-digital converters (ADCs) with true bipolar inputs. Each channel contains a sample-and-hold circuit that allows simultaneous high-speed multi-channel signal acquisition.
The ADS855x supports data rates of up to 730 kSPS in parallel interface mode or up to 500 kSPS if the serial interface is used. The bus width of the parallel interface can be set to eight or 16 bits. In serial mode, up to three output channels can be activated.
The ADS855x is specified over the full industrial temperature range of –40°C to 125°C and is available in an LQFP-64 package.
||BODY SIZE (NOM)
||10.00 mm × 10.00 mm
- For all available packages, see the orderable addendum at the end of the data sheet.
SNR vs Temperature
4 Revision History
Changes from C Revision (November 2015) to D Revision
Moved Electrical Characteristics: General table to before other Electrical Characteristics tablesGo
Added text reference for Figure 42 Go
Changed Figure 43: changed capacitor values from 820 nF to 820 pFGo
Changes from B Revision (January 2012) to C Revision
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Changes from A Revision (August 2009) to B Revision
Changed unit column for all tCONV rows in the Serial Interface Timing Requirements tableGo
Added tS3 row to Serial Interface Timing Requirements tableGo
Changed unit column for all tCONV rows in Parallel Interface Timing Requirements (Read Access) tableGo
Updated Figure 2Go
Updated Figure 3Go
Changed second paragraph of CONVST_x sectionGo
Changed minimum bandwidth value in last sentence of Reference sectionGo
Updated Figure 38Go