SPRS695D September   2011  – January 2016 AM3871 , AM3874

PRODUCTION DATA.  

  1. 1High-Performance System-on-Chip (SoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
    1. 2.1  Device Comparison
    2. 2.2  Device Characteristics
    3. 2.3  Device Compatibility
    4. 2.4  ARM Cortex-A8 Microprocessor Unit (MPU) Subsystem Overview
      1. 2.4.1 ARM Cortex-A8 RISC Processor
      2. 2.4.2 Embedded Trace Module (ETM)
      3. 2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 2.4.4 ARM Cortex-A8 PLL (PLL_ARM)
      5. 2.4.5 ARM MPU Interconnect
    5. 2.5  Media Controller Overview
    6. 2.6  SGX530 Overview
    7. 2.7  Spinlock Module Overview
    8. 2.8  Mailbox Module Overview
    9. 2.9  Memory Map Summary
      1. 2.9.1 L3 Memory Map
      2. 2.9.2 L4 Memory Map
        1. 2.9.2.1 L4 Fast Peripheral Memory Map
        2. 2.9.2.2 L4 Slow Peripheral Memory Map
      3. 2.9.3 DDR DMM TILER Extended Addressing Map
    10. 2.10 Pin Maps
    11. 2.11 Terminal Functions
      1. 2.11.1  Boot Configuration
      2. 2.11.2  Camera Interface (I/F)
      3. 2.11.3  Controller Area Network (DCAN) Modules (DCAN0, DCAN1)
      4. 2.11.4  DDR2/DDR3 Memory Controller
      5. 2.11.5  EDMA
      6. 2.11.6  EMAC [(R)(G)MII Modes] and MDIO
      7. 2.11.7  General-Purpose Input/Outputs (GPIOs)
      8. 2.11.8  GPMC
      9. 2.11.9  HDMI
      10. 2.11.10 I2C
      11. 2.11.11 McASP
      12. 2.11.12 McBSP
      13. 2.11.13 PCI-Express (PCIe)
      14. 2.11.14 Reset, Interrupts, and JTAG Interface
      15. 2.11.15 Serial ATA (SATA) Signals
      16. 2.11.16 SD Signals (MMC/SD/SDIO)
      17. 2.11.17 SPI
      18. 2.11.18 Oscillator/PLL, Audio Reference Clocks, and Clock Generator
      19. 2.11.19 Timer
      20. 2.11.20 UART
      21. 2.11.21 USB
      22. 2.11.22 Video Input (Digital)
      23. 2.11.23 Video Output (Digital)
      24. 2.11.24 Video Output (Analog, TV)
      25. 2.11.25 Reserved Pins
      26. 2.11.26 Supply Voltages
      27. 2.11.27 Ground Pins (VSS)
  3. 3Device Configurations
    1. 3.1 Control Module Registers
    2. 3.2 Boot Modes
      1. 3.2.1 XIP (NOR) Boot Options
      2. 3.2.2 NAND Flash Boot
      3. 3.2.3 NAND I2C Boot (I2C EEPROM)
      4. 3.2.4 MMC/SD Cards Boot
      5. 3.2.5 SPI Boot
      6. 3.2.6 Ethernet PHY Mode Selection
      7. 3.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)
      8. 3.2.8 UART Bootmode
    3. 3.3 Pin Multiplexing Control
    4. 3.4 Handling Unused Pins
    5. 3.5 DeBugging Considerations
      1. 3.5.1 Pullup/Pulldown Resistors
  4. 4 System Interconnect
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
    5. 5.5 Thermal Resistance Characteristics (PBGA Package) [CYE-04] (Thinner Top Hat)
  6. 6Power, Reset, Clocking, and Interrupts
    1. 6.1 Power, Reset and Clock Management (PRCM) Module
    2. 6.2 Power
      1. 6.2.1 Voltage and Power Domains
        1. 6.2.1.1 Core Logic Voltage Domains
        2. 6.2.1.2 Memory Voltage Domains
        3. 6.2.1.3 Power Domains
      2. 6.2.2 SmartReflex [Not Supported]
        1. 6.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)
        2. 6.2.2.2 Adaptive Voltage Scaling [Not Supported]
      3. 6.2.3 Memory Power Management
      4. 6.2.4 SERDES_CLKP and SERDES_CLKN LDO
      5. 6.2.5 Dual Voltage I/Os
      6. 6.2.6 I/O Power-Down Modes
      7. 6.2.7 Standby Mode
      8. 6.2.8 Supply Sequencing
        1. 6.2.8.1 Power-Up Sequence
        2. 6.2.8.2 Power-Down Sequence
      9. 6.2.9 Power-Supply Decoupling
        1. 6.2.9.1 Analog and PLL
        2. 6.2.9.2 Digital
    3. 6.3 Reset
      1. 6.3.1  System-Level Reset Sources
      2. 6.3.2  Power-on Reset (POR pin)
      3. 6.3.3  External Warm Reset (RESET pin)
      4. 6.3.4  Emulation Warm Reset
      5. 6.3.5  Watchdog Reset
      6. 6.3.6  Software Global Cold Reset
      7. 6.3.7  Software Global Warm Reset
      8. 6.3.8  Test Reset (TRST pin)
      9. 6.3.9  Local Reset
      10. 6.3.10 Reset Priority
      11. 6.3.11 Reset Status Register
      12. 6.3.12 PCIE Reset Isolation
      13. 6.3.13 EMAC Switch Reset Isolation
      14. 6.3.14 RSTOUT_WD_OUT Pin
      15. 6.3.15 Effect of Reset on Emulation and Trace
      16. 6.3.16 Reset During Power Domain Switching
      17. 6.3.17 Pin Behaviors at Reset
      18. 6.3.18 Reset Electrical Data/Timing
    4. 6.4 Clocking
      1. 6.4.1  Device (DEV) and Auxiliary (AUX) Clock Inputs
        1. 6.4.1.1 Using the Internal Oscillators
        2. 6.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input
      2. 6.4.2  SERDES_CLKN/P Input Clock
      3. 6.4.3  AUD_CLKINx Input Clocks
      4. 6.4.4  CLKIN32 Input Clock
      5. 6.4.5  External Input Clocks
      6. 6.4.6  Output Clocks Select Logic
      7. 6.4.7  Input/Output Clocks Electrical Data/Timing
      8. 6.4.8  PLLs
        1. 6.4.8.1 PLL Power Supply Filtering
        2. 6.4.8.2 PLL Multipliers and Dividers
        3. 6.4.8.3 PLL Frequency Limits
        4. 6.4.8.4 PLL Register Descriptions
      9. 6.4.9  SYSCLKs
      10. 6.4.10 Module Clocks
    5. 6.5 Interrupts
      1. 6.5.1 ARM Cortex-A8 Interrupts
  7. 7 Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 7.1.2 3.3-V Signal Transition Rates
      3. 7.1.3 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Controller Area Network Interface (DCAN)
      1. 7.3.1 DCAN Peripheral Register Descriptions
      2. 7.3.2 DCAN Electrical Data/Timing
    4. 7.4  EDMA
      1. 7.4.1 EDMA Channel Synchronization Events
      2. 7.4.2 EDMA Peripheral Register Descriptions
    5. 7.5  Emulation Features and Capability
      1. 7.5.1 Advanced Event Triggering (AET)
      2. 7.5.2 Trace
      3. 7.5.3 IEEE 1149.1 JTAG
        1. 7.5.3.1 JTAG ID (JTAGID) Register Description
        2. 7.5.3.2 JTAG Electrical Data/Timing
    6. 7.6  Ethernet MAC Switch (EMAC SW)
      1. 7.6.1 EMAC Peripheral Register Descriptions
      2. 7.6.2 EMAC Electrical Data/Timing
        1. 7.6.2.1 EMAC MII and GMII Electrical Data/Timing
        2. 7.6.2.2 EMAC RMII Electrical Data/Timing
        3. 7.6.2.3 EMAC RGMII Electrical Data/Timing
      3. 7.6.3 Management Data Input/Output (MDIO)
        1. 7.6.3.1 MDIO Peripheral Register Descriptions
        2. 7.6.3.2 MDIO Electrical Data/Timing
    7. 7.7  General-Purpose Input/Output (GPIO)
      1. 7.7.1 GPIO Peripheral Register Descriptions
      2. 7.7.2 GPIO Electrical Data/Timing
    8. 7.8  General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
      1. 7.8.1 GPMC and ELM Peripherals Register Descriptions
      2. 7.8.2 GPMC Electrical Data/Timing
        1. 7.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        2. 7.8.2.2 GPMC/NOR Flash Interface Asynchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        3. 7.8.2.3 GPMC/NAND Flash and ELM Interface Timing
    9. 7.9  High-Definition Multimedia Interface (HDMI)
      1. 7.9.1 HDMI Design Guidelines
        1. 7.9.1.1 HDMI Interface Schematic
        2. 7.9.1.2 TMDS Routing
        3. 7.9.1.3 DDC Signals
        4. 7.9.1.4 HDMI ESD Protection Device (Required)
        5. 7.9.1.5 PCB Stackup Specifications
        6. 7.9.1.6 Grounding
    10. 7.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 7.10.1 HDVPSS Electrical Data/Timing
      2. 7.10.2 Video DAC Guidelines and Electrical Data/Timing
    11. 7.11 Inter-Integrated Circuit (I2C)
      1. 7.11.1 I2C Peripheral Register Descriptions
      2. 7.11.2 I2C Electrical Data/Timing
    12. 7.12 Imaging Subsystem (ISS)
      1. 7.12.1 ISSCAM Electrical Data/Timing
    13. 7.13 DDR2/DDR3 Memory Controller
      1. 7.13.1 DDR2/3 Memory Controller Register Descriptions
      2. 7.13.2 DDR2/DDR3 PHY Register Descriptions
      3. 7.13.3 DDR-Related Control Module Registers Description
      4. 7.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing
        1. 7.13.4.1 DDR2 Routing Specifications
          1. 7.13.4.1.1 DDR2 Interface
            1. 7.13.4.1.1.1  DDR2 Interface Schematic
            2. 7.13.4.1.1.2  Compatible JEDEC DDR2 Devices
            3. 7.13.4.1.1.3  PCB Stackup
            4. 7.13.4.1.1.4  Placement
            5. 7.13.4.1.1.5  DDR2 Keepout Region
            6. 7.13.4.1.1.6  Bulk Bypass Capacitors
            7. 7.13.4.1.1.7  High-Speed Bypass Capacitors
            8. 7.13.4.1.1.8  Net Classes
            9. 7.13.4.1.1.9  DDR2 Signal Termination
            10. 7.13.4.1.1.10 VREFSSTL_DDR Routing
          2. 7.13.4.1.2 DDR2 CK and ADDR_CTRL Routing
        2. 7.13.4.2 DDR3 Routing Specifications
          1. 7.13.4.2.1 DDR3 versus DDR2
          2. 7.13.4.2.2 DDR3 EMIFs
          3. 7.13.4.2.3 DDR3 Device Combinations
          4. 7.13.4.2.4 DDR3 Interface Schematic
            1. 7.13.4.2.4.1  Compatible JEDEC DDR3 Devices
            2. 7.13.4.2.4.2  PCB Stackup
            3. 7.13.4.2.4.3  Placement
            4. 7.13.4.2.4.4  DDR3 Keepout Region
            5. 7.13.4.2.4.5  Bulk Bypass Capacitors
            6. 7.13.4.2.4.6  High-Speed Bypass Capacitors
              1. 7.13.4.2.4.6.1 Return Current Bypass Capacitors and Vias
            7. 7.13.4.2.4.7  Net Classes
            8. 7.13.4.2.4.8  DDR3 Signal Termination
            9. 7.13.4.2.4.9  VREFSSTL_DDR Routing
            10. 7.13.4.2.4.10 VTT
            11. 7.13.4.2.4.11 CK and ADDR_CTRL Topologies and Routing Definition
              1. 7.13.4.2.4.11.1 Four DDR3 Devices
                1. 7.13.4.2.4.11.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 7.13.4.2.4.11.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              2. 7.13.4.2.4.11.2 Two DDR3 Devices
                1. 7.13.4.2.4.11.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 7.13.4.2.4.11.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              3. 7.13.4.2.4.11.3 One DDR3 Device
                1. 7.13.4.2.4.11.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 7.13.4.2.4.11.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
            12. 7.13.4.2.4.12 Data Topologies and Routing Definition
              1. 7.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
              2. 7.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
            13. 7.13.4.2.4.13 Routing Specification
              1. 7.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification
              2. 7.13.4.2.4.13.2 DQS and DQ Routing Specification
    14. 7.14 Multichannel Audio Serial Port (McASP)
      1. 7.14.1 McASP Device-Specific Information
      2. 7.14.2 McASP0, McASP1, McASP2, McASP3, McASP4, and McASP5 Peripheral Registers Descriptions
      3. 7.14.3 McASP (McASP[5:0]) Electrical Data/Timing
    15. 7.15 Multichannel Buffered Serial Port (McBSP)
      1. 7.15.1 McBSP Peripheral Register Descriptions
      2. 7.15.2 McBSP Electrical Data/Timing
    16. 7.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
      1. 7.16.1 MMC/SD/SDIO Peripheral Register Descriptions
      2. 7.16.2 MMC/SD/SDIO Electrical Data/Timing
    17. 7.17 Peripheral Component Interconnect Express (PCIe)
      1. 7.17.1 PCIe Peripheral Register Descriptions
      2. 7.17.2 PCIe Electrical Data/Timing
      3. 7.17.3 PCIe Design and Layout Guidelines
        1. 7.17.3.1 Clock Source
        2. 7.17.3.2 PCIe Connections and Interface Compliance
          1. 7.17.3.2.1 Coupling Capacitors
          2. 7.17.3.2.2 Polarity Inversion
        3. 7.17.3.3 Nonstandard PCIe Connections
          1. 7.17.3.3.1 PCB Stackup Specifications
          2. 7.17.3.3.2 Routing Specifications
    18. 7.18 Serial ATA Controller (SATA)
      1. 7.18.1 SATA Peripheral Register Descriptions
      2. 7.18.2 SATA Interface Design Guidelines
        1. 7.18.2.1 SATA Interface Schematic
        2. 7.18.2.2 Compatible SATA Components and Modes
        3. 7.18.2.3 PCB Stackup Specifications
        4. 7.18.2.4 Routing Specifications
        5. 7.18.2.5 Coupling Capacitors
    19. 7.19 Serial Peripheral Interface (SPI)
      1. 7.19.1 SPI Peripheral Register Descriptions
      2. 7.19.2 SPI Electrical Data/Timing
    20. 7.20 Timers
      1. 7.20.1 Timer Peripheral Register Descriptions
      2. 7.20.2 Timer Electrical/Data Timing
    21. 7.21 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.21.1 UART Peripheral Register Descriptions
      2. 7.21.2 UART Electrical/Data Timing
    22. 7.22 Universal Serial Bus (USB2.0)
      1. 7.22.1 USB2.0 Peripheral Register Descriptions
      2. 7.22.2 USB2.0 Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CYE|684
サーマルパッド・メカニカル・データ
発注情報

Device Overview

2.1 Device Comparison

Table 2-1 shows a comparison between devices, highlighting the differences.

Table 2-1 AM387x Device Comparison

FEATURES DEVICES
AM3874 AM3871
HDVPSS Video Ports (Inputs) VIN[0]/VIN[1] NONE
Video Ports (Outputs) VOUT[0]/VOUT[1] NONE
HDMI YES (1) NONE
SGX530 YES (1) NONE

2.2 Device Characteristics

Table 2-2 provides an overview of the AM387x Sitara™ ARM Processors , which includes significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 2-2 Characteristics of the Processor

HARDWARE FEATURES AM387x
Peripherals


Not all peripherals pins are available at the same time (for more details, see the Device Configurations section). 		HD Video Processing Subsystem (HDVPSS) 1 16-/24-bit HD Capture Port or
2 8-bit SD Capture Ports
and
1 8-bit SD Capture Port
and
1 16-/24-/30-bit HD Display Port or
1 8-/16-/24-bit HD Capture Port
and
1 16-24-bit HD Display Port
and
1 HDMI 1.3 Transmitter
and
2 SD Video DACs
Imaging Subsystem (ISS) 1 Parallel Camera Input for Raw (up to 16-bit)
and BT.656/BT.1120 (8/16-bit)
DDR2/3 Memory Controller 2 (32-bit Bus Widths)
GPMC + ELM Asynchronous (8-/16-bit bus width)
RAM, NOR, NAND
EDMA 64 Independent Channels
8 QDMA Channels
10/100/1000 Ethernet MAC Switch with Management Data Input/Output (MDIO) 1 (with 2 MII/RMII/GMII/RGMII Interfaces)
USB 2.0 2 (Supports High- and Full-Speed as a Device and
High-, Full-, and Low-Speed as a Host, or OTG)
PCI-Express 2.0 1 Port (1 5.0GT/s lane)
Timers 8 (32-bit General purpose)
and
1 (System Watchdog)
UART 6 (with SIR, MIR, FIR, CIR support and RTS/CTS flow control)
(UART0 Supports Modem Interface)
SPI 4 (Supports 4 slave devices)
MMC/SD/SDIO 1 (1-bit or 4-bit or 8-bit modes)
and
1 (8-bit mode) or
2 (1-bit or 4-bit modes)
I2C 4 (Master/Slave)
Media Controller Controls HDVPSS and ISS
McASP 6 (10/10/4/4/4/4 Serializers, Each with Transmit/Receive and DIT capability)
McBSP 1 (2 Data Pins, Transmit/Receive)
Controller Area Network (DCAN) 2
Serial ATA (SATA) 3.0 Gbps 1 (Supports 1 Hard Disk Drive)
RTC 1
GPIO Up to 128 pins
Parallel Camera Interface (CAM) 1
Spin Lock Module 1 (up to 128 H/W Semaphores)
Mailbox Module 1 (with 12 Mailboxes)
Size (Bytes) 768KB RAM, 48KB ROM
On-Chip Memory Organization ARM
32KB I-cache
32KB D-cache
512KB L2 Cache
64KB RAM
48KB Boot ROM
ADDITIONAL SHARED MEMORY
128KB On-chip RAM
ARM® Cortex®-A8 Main ID Register Variant/Revision r3p2
JTAG BSDL ID DEVICE_ID Register (address location: 0x4814_0600) see Section 7.5.3.1, JTAG ID (JTAGID) Register Description
CPU Frequency MHz ARM Cortex-A8 1000, 720 MHZ
Cycle Time ns ARM Cortex -A8 1.0, 1.39 ns
Voltage Core Logic (V) OPP100, OPP120 1.10 V – 1.20 V
OPP166 1.35 V
I/O (V) 1.5 V, 1.8 V, 3.3 V
Package 23 x 23 mm [Flip Chip Ball Grid Array (FCBGA)] 684-Pin BGA (CYE) [with Via Channel Technology]
Process Technology μm 0.045 μm
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

2.3 Device Compatibility

2.4 ARM Cortex-A8 Microprocessor Unit (MPU) Subsystem Overview

The ARM Cortex-A8 Subsystem is designed to give the ARM Cortex-A8 Master control of the device. In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystems, peripherals, and external memories.

The ARM Cortex-A8 Subsystem includes the following features:

  • ARM Cortex-A8 RISC processor:
    • ARMv7 ISA plus Thumb2™, JazelleX™, and Media Extensions
    • Neon™ Floating-Point Unit
    • Enhanced Memory Management Unit (MMU)
    • Little Endian
    • 32KB L1 Instruction Cache
    • 32KB L1 Data Cache
    • 512KB L2 Cache
  • CoreSight Embedded Trace Module (ETM)
  • ARM Cortex-A8 Interrupt Controller (AINTC)
  • Embedded PLL Controller (PLL_ARM)
  • 64KB Internal RAM
  • 48KB Internal Public ROM

Figure 2-1 shows the ARM Cortex-A8 Subsystem for the device.

AM3874 AM3871 dg_arm_subsys_nonsec_prs647.gif Figure 2-1 ARM Cortex-A8 Subsystem

For more details on the ARM Cortex-A8 Subsystem, see the System MMU section of the Chip Level Resources chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

2.4.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 Subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose microprocessors. This processor is targeted at multitasking applications where full memory management, high performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem, including:

  • ARM Cortex-A8 Integer Core
  • Superscalar ARMv7 Instruction Set
  • Thumb-2 Instruction Set
  • Jazelle RCT Acceleration
  • CP14 Debug Coprocessor
  • CP15 System Control Coprocessor
  • NEON™ 64-/128-bit Hybrid SIMD Engine for Multimedia
  • Enhanced VFPv3 Floating-Point Coprocessor
  • Enhanced Memory Management Unit (MMU)
  • Separate Level-1 Instruction and Data Caches
  • Integrated Level-2 Cache
  • 128-bit Interconnector-to-System Memories and Peripherals
  • Embedded Trace Module (ETM).

2.4.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts:

  • The Trace port which provides real-time trace capability for the ARM Cortex-A8.
  • Triggering facilities that provide trigger resources, which include address and data comparators, counter, and sequencers.

The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

For more details on the ETM, see Section 7.5.2, Trace.

2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 6.5.1, ARM Cortex-A8 Interrupts.

Note: For General-Purpose devices, the AINTC does not support the generation of FIQs to the ARM processor.

2.4.4 ARM Cortex-A8 PLL (PLL_ARM)

The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the subsystem’s clocks from the DEV Clock input. For more details on the PLL_ARM, see Section 6.4, Clocking.

2.4.5 ARM MPU Interconnect

The ARM Cortex-A8 processor is connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128 bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64 bits wide and provides access to the remaining device modules.

2.5 Media Controller Overview

The Media Controller has the responsibility of managing the HDVPSS and ISS modules.

For more details on the Media Controller, see the Media Controller Subsystem section of the Chip Level Resources chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

2.6 SGX530 Overview

The SGX530 is a vector/3D graphics accelerator for vector and 3-dimensional (3D) graphics applications. The SGX530 graphics accelerator efficiently processes a number of various multimedia data types concurrently:

  • Pixel data
  • Vertex data
  • Video data

This is achieved using a multithreaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching.

The SGX530 has the following major features:

  • Vector graphics and 3D graphics
  • Tile-based architecture
  • USSE - multithreaded engine incorporating pixel and vertex shader functionality
  • Advanced shader feature set - in excess of Microsoft VS3.0, PS3.0, and OpenGL2.0
  • Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1
  • Fine-grained task switching, load balancing, and power management
  • Advanced geometry DMA driven operation for minimum CPU interaction
  • Programmable high-quality image anti-aliasing
  • POWERVR® SGX core MMU for address translation from the core virtual address to the external physical address (up to 4GB address range)
  • Fully-virtualized memory addressing for OS operation in a unified memory architecture
  • Advanced and standard 2D operations [for example, vector graphics, block level transfers (BLTs), raster operations (ROPs)]

For more details on the SGX530, see the Chip Level Resources chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

2.7 Spinlock Module Overview

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple processors in the device:

  • ARM Cortex-A8 processor
  • Media Controller

The Spinlock module implements 128 spinlocks (or hardware semaphores) that provide an efficient way to perform a lock operation of a device resource using a single read-access, avoiding the need for a read-modify-write bus transfer of which the programmable cores are not capable.

For more details on the Spinlock Module, see the Spinlock section of the Chip Level Resources chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

2.8 Mailbox Module Overview

The device Mailbox module facilitates communication between the ARM Cortex-A8 and the Media Controller. The device mailbox consists of twelve mailboxes, each supporting a 1-way communication between two of the above processors. The sender sends information to the receiver by writing a message to the mailbox registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender about an overflow situation.

The Mailbox module supports the following features (see Figure 2-2):

  • 12 mailboxes
  • Flexible mailbox-to-processor assignment scheme
  • Four-message FIFO depth for each message queue
  • 32-bit message width
  • Message reception and queue-not-full notification using interrupts
  • Three interrupts (one to ARM Cortex-A8 and two to Media Controller)
AM3874 AM3871 mailbox_bd_sprs681.gif Figure 2-2 Mailbox Module Block Diagram

For more details on the Mailbox Module, see the Mailbox section of the Chip Level Resources chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

2.9 Memory Map Summary

The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.

2.9.1 L3 Memory Map

Table 2-3 shows the L3 memory map for all system masters (including Cortex-A8).

For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see Section 4, System Interconnect.

Table 2-3 L3 Memory Map

START ADDRESS
(HEX)		 END ADDRESS
(HEX)		 SIZE DESCRIPTION
0x0000_0000 0x00FF_FFFF 16MB GPMC (Reserved for BOOTROM)
0x0100_0000 0x1FFF_FFFF 496MB GPMC
0x2000_0000 0x2FFF_FFFF 256MB PCIe
0x3000_0000 0x3FFF_FFFF 256MB Reserved
0x4000_0000 0x4001_FFFF 128KB Reserved
0x4002_0000 0x4002_BFFF 48KB ARM Cortex-A8 ROM
(Accessible by ARM Cortex-A8 only)
0x4002_C000 0x402E_FFFF 2832KB Reserved
0x402F_0000 0x402F_03FF 1KB Reserved
0x402F_0400 0x402F_FFFF 64KB - 1KB ARM Cortex-A8 RAM
(Accessible by ARM Cortex-A8 only)
0x4030_0000 0x4031_FFFF 128KB OCMC SRAM
0x4032_0000 0x407F_FFFF 4992KB Reserved
0x4080_0000 0x4083_FFFF 256KB Reserved
0x4084_0000 0x40DF_FFFF 5888KB Reserved
0x40E0_0000 0x40E0_7FFF 32KB Reserved
0x40E0_8000 0x40EF_FFFF 992KB Reserved
0x40F0_0000 0x40F0_7FFF 32KB Reserved
0x40F0_8000 0x40FF_FFFF 992KB Reserved
0x4100_0000 0x41FF_FFFF 16MB Reserved
0x4200_0000 0x43FF_FFFF 32MB Reserved
0x4400_0000 0x443F_FFFF 4MB L3 Fast configuration registers
0x4440_0000 0x447F_FFFF 4MB L3 Mid configuration registers
0x4480_0000 0x44BF_FFFF 4MB L3 Slow configuration registers
0x44C0_0000 0x45FF_FFFF 20MB Reserved
0x4600_0000 0x463F_FFFF 4MB McASP0 Data Peripheral Registers
0x4640_0000 0x467F_FFFF 4MB McASP1 Data Peripheral Registers
0x4680_0000 0x46BF_FFFF 4MB McASP2 Data Peripheral Registers
0x46C0_0000 0x46FF_FFFF 4MB HDMI
0x4700_0000 0x473F_FFFF 4MB McBSP
0x4740_0000 0x477F_FFFF 4MB USB
0x4780_0000 0x4780_FFFF 64KB Reserved
0x4781_0000 0x4781_1FFF 8KB MMC/SD/SDIO2 Peripheral Registers
0x4781_2000 0x47BF_FFFF 4MB - 72KB Reserved
0x47C0_0000 0x47C0_BFFF 48KB Reserved
0x47C0_C000 0x47C0_C3FF 1KB Reserved
0x47C0_C400 0x47C0_C7FF 1KB DDR0 PHY Registers
0x47C0_C800 0x47C0_CBFF 1KB DDR1 PHY Registers
0x47C0_CC00 0x47C0_CFFF 1KB Reserved
0x47C0_D000 0x47FF FFFF 4044KB Reserved
0x4800_0000 0x48FF_FFFF 16MB L4 Slow Peripheral Domain
(see Table 2-5)
0x4900_0000 0x490F_FFFF 1MB EDMA TPCC Registers
0x4910_0000 0x497F_FFFF 7MB Reserved
0x4980_0000 0x498F_FFFF 1MB EDMA TPTC0 Registers
0x4990_0000 0x499F_FFFF 1MB EDMA TPTC1 Registers
0x49A0_0000 0x49AF_FFFF 1MB EDMA TPTC2 Registers
0x49B0_0000 0x49BF_FFFF 1MB EDMA TPTC3 Registers
0x49C0_0000 0x49FF_FFFF 4MB Reserved
0x4A00_0000 0x4AFF_FFFF 16MB L4 Fast Peripheral Domain
(see Table 2-4)
0x4B00_0000 0x4BFF_FFFF 16MB Emulation Subsystem
0x4C00_0000 0x4CFF_FFFF 16MB DDR0 Registers
0x4D00_0000 0x4DFF_FFFF 16MB DDR1 Registers
0x4E00_0000 0x4FFF_FFFF 32MB DDR DMM Registers
0x5000_0000 0x50FF_FFFF 16MB GPMC Registers
0x5100_0000 0x51FF_FFFF 16MB PCIE Registers
0x5200_0000 0x54FF_FFFF 48MB Reserved
0x5500_0000 0x55FF_FFFF 16MB Media Controller
0x5600_0000 0x56FF_FFFF 16MB SGX530
0x5700_0000 0x57FF_FFFF 16MB Reserved
0x5800_0000 0x5BFF_FFFF 64MB Reserved
0x5C00_0000 0x5DFF_FFFF 32MB ISS
0x5E00_0000 0x5FFF_FFFF 32MB Reserved
0x6000_0000 0x7FFF_FFFF 512MB DDR DMM TILER Window (see Table 2-6)
0x8000_0000 0xFFFF_FFFF 2GB DDR
0x1 0000 0000 0x1 FFFF FFFF 4GB DDR DMM TILER Extended Address Map
(ISS and HDVPSS only) [see Table 2-6]

2.9.2 L4 Memory Map

The L4 Fast Peripheral Domain, L4 Slow Peripheral Domain regions of the memory maps above are broken out into Table 2-4 and Table 2-5.

For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see Section 4, System Interconnect.

2.9.2.1 L4 Fast Peripheral Memory Map

Table 2-4 L4 Fast Peripheral Memory Map

Cortex-A8 and L3 Masters SIZE DEVICE NAME
START ADDRESS
(HEX)		 END ADDRESS
(HEX)
0x4A00_0000 0x4A00_07FF 2KB L4 Fast Configuration - Address/Protection (AP)
0x4A00_0800 0x4A00_0FFF 2KB L4 Fast Configuration - Link Agent (LA)
0x4A00_1000 0x4A00_13FF 1KB L4 Fast Configuration - Initiator Port (IP0)
0x4A00_1400 0x4A00_17FF 1KB L4 Fast Configuration - Initiator Port (IP1)
0x4A00_1800 0x4A00_1FFF 2KB Reserved
0x4A00_2000 0x4A07_FFFF 504KB Reserved
0x4A08_0000 0x4A0F_FFFF 512KB Reserved
0x4A10_0000 0x4A10_7FFF 32KB EMAC SW Peripheral Registers
0x4A10_8000 0x4A10_8FFF 4KB EMAC SW Support Registers
0x4A14_0000 0x4A14_FFFF 64KB SATA Peripheral Registers
0x4A15_0000 0x4A15_0FFF 4KB SATA Support Registers
0x4A15_1000 0x4A17_FFFF 188KB Reserved
0x4A18_0000 0x4A1A_1FFF 136KB Reserved
0x4A1A_2000 0x4A1A_3FFF 8KB McASP3 Configuration Peripheral Registers
0x4A1A_4000 0x4A1A_4FFF 4KB McASP3 Configuration Support Registers
0x4A1A_5000 0x4A1A_5FFF 4KB McASP3 Data Peripheral Registers
0x4A1A_6000 0x4A1A_6FFF 4KB McASP3 Data Support Registers
0x4A1A_7000 0x4A1A_7FFF 4KB Reserved
0x4A1A_8000 0x4A1A_9FFF 8KB McASP4 Configuration Peripheral Registers
0x4A1A_A000 0x4A1A_AFFF 4KB McASP4 Configuration Support Registers
0x4A1A_B000 0x4A1A_BFFF 4KB McASP4 Data Peripheral Registers
0x4A1A_C000 0x4A1A_CFFF 4KB McASP4 Data Support Registers
0x4A1A_D000 0x4A1A_DFFF 4KB Reserved
0x4A1A_E000 0x4A1A_FFFF 8KB McASP5 Configuration Peripheral Registers
0x4A1B_0000 0x4A1B_0FFF 4KB McASP5 Configuration Support Registers
0x4A1B_1000 0x4A1B_1FFF 4KB McASP5 Data Peripheral Registers
0x4A1B_2000 0x4A1B_2FFF 4KB McASP5 Data Support Registers
0x4A1B_3000 0x4A1B_5FFF 12KB Reserved
0x4A1B_6000 0x4A1B_6FFF 4KB Reserved
0x4A1B_4000 0x4AFF_FFFF 14632KB Reserved

2.9.2.2 L4 Slow Peripheral Memory Map

Table 2-5 L4 Slow Peripheral Memory Map

(1) These regions decoded internally by the Cortex-A8 Subsystem and are not physically part of the L4 Slow. They are included here only for reference when considering the Cortex-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.
Cortex-A8 and L3 Masters SIZE DEVICE NAME
START ADDRESS
(HEX)		 END ADDRESS
(HEX)
0x4800_0000 0x4800_07FF 2KB L4 Slow Configuration – Address/Protection (AP)
0x4800_0800 0x4800_0FFF 2KB L4 Slow Configuration – Link Agent (LA)
0x4800_1000 0x4800_13FF 1KB L4 Slow Configuration – Initiator Port (IP0)
0x4800_1400 0x4800_17FF 1KB L4 Slow Configuration – Initiator Port (IP1)
0x4800_1800 0x4800_1FFF 2KB Reserved
0x4800_2000 0x4800_7FFF 24KB Reserved
0x4800_8000 0x4800_8FFF 32KB Reserved
0x4801_0000 0x4801_0FFF 4KB Reserved
0x4801_1000 0x4801_1FFF 4KB Reserved
0x4801_2000 0x4801_FFFF 56KB Reserved
0x4802_0000 0x4802_0FFF 4KB UART0 Peripheral Registers
0x4802_1000 0x4802_1FFF 4KB UART0 Support Registers
0x4802_2000 0x4802_2FFF 4KB UART1 Peripheral Registers
0x4802_3000 0x4802_3FFF 4KB UART1 Support Registers
0x4802_4000 0x4802_4FFF 4KB UART2 Peripheral Registers
0x4802_5000 0x4802_5FFF 4KB UART2 Support Registers
0x4802_6000 0x4802_7FFF 8KB Reserved
0x4802_8000 0x4802_8FFF 4KB I2C0 Peripheral Registers
0x4802_9000 0x4802_9FFF 4KB I2C0 Support Registers
0x4802_A000 0x4802_AFFF 4KB I2C1 Peripheral Registers
0x4802_B000 0x4802_BFFF 4KB I2C1 Support Registers
0x4802_C000 0x4802_DFFF 8KB Reserved
0x4802_E000 0x4802_EFFF 4KB TIMER1 Peripheral Registers
0x4802_F000 0x4802_FFFF 4KB TIMER1 Support Registers
0x4803_0000 0x4803_0FFF 4KB SPI0 Peripheral Registers
0x4803_1000 0x4803_1FFF 4KB SPI0 Support Registers
0x4803_2000 0x4803_2FFF 4KB GPIO0 Peripheral Registers
0x4803_3000 0x4803_3FFF 4KB GPIO0 Support Registers
0x4803_4000 0x4803_7FFF 16KB Reserved
0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Peripheral Registers
0x4803_A000 0x4803_AFFF 4KB McASP0 CFG Support Registers
0x4803_B000 0x4803_BFFF 4KB Reserved
0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Peripheral Registers
0x4803_E000 0x4803_EFFF 4KB McASP1 CFG Support Registers
0x4803_F000 0x4803_FFFF 4KB Reserved
0x4804_0000 0x4804_0FFF 4KB TIMER2 Peripheral Registers
0x4804_1000 0x4804_1FFF 4KB TIMER2 Support Registers
0x4804_2000 0x4804_2FFF 4KB TIMER3 Peripheral Registers
0x4804_3000 0x4804_3FFF 4KB TIMER3 Support Registers
0x4804_4000 0x4804_4FFF 4KB TIMER4 Peripheral Registers
0x4804_5000 0x4804_5FFF 4KB TIMER4 Support Registers
0x4804_6000 0x4804_6FFF 4KB TIMER5 Peripheral Registers
0x4804_7000 0x4804_7FFF 4KB TIMER5 Support Registers
0x4804_8000 0x4804_8FFF 4KB TIMER6 Peripheral Registers
0x4804_9000 0x4804_9FFF 4KB TIMER6 Support Registers
0x4804_A000 0x4804_AFFF 4KB TIMER7 Peripheral Registers
0x4804_B000 0x4804_BFFF 4KB TIMER7 Support Registers
0x4804_C000 0x4804_CFFF 4KB GPIO1 Peripheral Registers
0x4804_D000 0x4804_DFFF 4KB GPIO1 Support Registers
0x4804_E000 0x4804_FFFF 8KB Reserved
0x4805_0000 0x4805_1FFF 8KB McASP2 CFG Peripheral Registers
0x4805_2000 0x4805_2FFF 4KB McASP2 CFG Support Registers
0x4805_3000 0x4805_FFFF 52KB Reserved
0x4806_0000 0x4806_FFFF 64KB MMC/SD/SDIO0 Peripheral Registers
0x4807_0000 0x4807_0FFF 4KB MMC/SD/SDIO0 Support Registers
0x4807_1000 0x4807_FFFF 60KB Reserved
0x4808_0000 0x4808_FFFF 64KB ELM Peripheral Registers
0x4809_0000 0x4809_0FFF 4KB ELM Support Registers
0x4809_1000 0x4809_FFFF 60KB Reserved
0x480A_0000 0x480A_FFFF 64KB Reserved
0x480B_0000 0x480B_0FFF 4KB Reserved
0x480B_1000 0x480B_FFFF 60KB Reserved
0x480C_0000 0x480C_0FFF 4KB RTC Peripheral Registers
0x480C_1000 0x480C_1FFF 4KB RTC Support Registers
0x480C_2000 0x480C_3FFF 8KB Reserved
0x480C_4000 0x480C_7FFF 16KB Reserved
0x480C_8000 0x480C_8FFF 4KB Mailbox Peripheral Registers
0x480C_9000 0x480C_9FFF 4KB Mailbox Support Registers
0x480C_A000 0x480C_AFFF 4KB Spinlock Peripheral Registers
0x480C_B000 0x480C_BFFF 4KB Spinlock Support Registers
0x480C_C000 0x480F_FFFF 208KB Reserved
0x4810_0000 0x4811_FFFF 128KB HDVPSS Peripheral Registers
0x4812_0000 0x4812_0FFF 4KB HDVPSS Support Registers
0x4812_1000 0x4812_1FFF 4KB Reserved
0x4812_2000 0x4812_2FFF 4KB HDMI Peripheral Registers
0x4812_3000 0x4812_3FFF 4KB HDMI Support Registers
0x4812_4000 0x4813_FFFF 112KB Reserved
0x4814_0000 0x4815_FFFF 128KB Control Module Peripheral Registers
0x4816_0000 0x4816_0FFF 4KB Control Module Support Registers
0x4816_1000 0x4817_FFFF 124KB Reserved
0x4818_0000 0x4818_2FFF 12KB PRCM Peripheral Registers
0x4818_3000 0x4818_3FFF 4KB PRCM Support Registers
0x4818_4000 0x4818_7FFF 16KB Reserved
0x4818_C000 0x4818_CFFF 4KB OCP Watchpoint Peripheral Registers
0x4818_D000 0x4818_DFFF 4KB OCP Watchpoint Support Registers
0x4818_E000 0x4818_EFFF 4KB Reserved
0x4818_F000 0x4818_FFFF 4KB Reserved
0x4819_0000 0x4819_3FFF 16KB Reserved
0x4819_4000 0x4819_BFFF 32KB Reserved
0x4819_C000 0x481F_FFFF 400KB Reserved
0x4819_C000 0x4819_CFFF 4KB I2C2 Peripheral Registers
0x4819_D000 0x4819_DFFF 4KB I2C2 Support Registers
0x4819_E000 0x4819_EFFF 4KB I2C3 Peripheral Registers
0x4819_F000 0x4819_FFFF 4KB I2C3 Support Registers
0x481A_0000 0x481A_0FFF 4KB SPI1 Peripheral Registers
0x481A_1000 0x481A_1FFF 4KB SPI1 Support Registers
0x481A_2000 0x481A_2FFF 4KB SPI2 Peripheral Registers
0x481A_3000 0x481A_3FFF 4KB SPI2 Support Registers
0x481A_4000 0x481A_4FFF 4KB SPI3 Peripheral Registers
0x481A_5000 0x481A_5FFF 4KB SPI3 Support Registers
0x481A_6000 0x481A_6FFF 4KB UART3 Peripheral Registers
0x481A_7000 0x481A_7FFF 4KB UART3 Support Registers
0x481A_8000 0x481A_8FFF 4KB UART4 Peripheral Registers
0x481A_9000 0x481A_9FFF 4KB UART4 Support Registers
0x481A_A000 0x481A_AFFF 4KB UART5 Peripheral Registers
0x481A_B000 0x481A_BFFF 4KB UART5 Support Registers
0x481A_C000 0x481A_CFFF 4KB GPIO2 Peripheral Registers
0x481A_D000 0x481A_DFFF 4KB GPIO2 Support Registers
0x481A_E000 0x481A_EFFF 4KB GPIO3 Peripheral Registers
0x481A_F000 0x481A_FFFF 4KB GPIO3 Support Registers
0x481B_0000 0x481B_FFFF 64KB Reserved
0x481C_0000 0x481C_0FFF 4KB Reserved
0x481C_1000 0x481C_1FFF 4KB TIMER8 Peripheral Registers
0x481C_2000 0x481C_2FFF 4KB TIMER8 Support Registers
0x481C_3000 0x481C_3FFF 4KB SYNCTIMER32K Peripheral Registers
0x481C_4000 0x481C_4FFF 4KB SYNCTIMER32K Support Registers
0x481C_5000 0x481C_5FFF 4KB PLLSS Peripheral Registers
0x481C_6000 0x481C_6FFF 4KB PLLSS
0x481C_7000 0x481C_7FFF 4KB WDT0 Peripheral Registers
0x481C_8000 0x481C_8FFF 4KB WDT0 Support Registers
0x481C_9000 0x481C_9FFF 8KB Reserved
0x481C_A000 0x481C_BFFF 8KB Reserved
0x481C_C000 0x481C_DFFF 8KB DCAN0 Peripheral Registers
0x481C_E000 0x481C_FFFF 8KB DCAN0 Support Registers
0x481D_0000 0x481D_1FFF 8KB DCAN1 Peripheral Registers
0x481D_2000 0x481D_3FFF 8KB DCAN1 Support Registers
0x481D_4000 0x481D_5FFF 8KB Reserved
0x481D_6000 0x481D_6FFF 4KB Reserved
0x481D_7000 0x481D_7FFF 4KB Reserved
0x481D_8000 0x481E_7FFF 64KB MMC/SD/SDIO1 Peripheral Registers
0x481E_8000 0x481E_8FFF 4KB MMC/SD/SDIO1 Support Registers
0x481E_9000 0x481F_FFFF 52KB Reserved
0x4820_0000 0x4820_0FFF 4KB Interrupt controller(1)
0x4820_1000 0x4823_FFFF 252KB Reserved(1)
0x4824_0000 0x4824_0FFF 4KB MPUSS config register(1)
0x4824_1000 0x4827_FFFF 252KB Reserved(1)
0x4828_0000 0x4828_0FFF 4KB Reserved(1)
0x4828_1000 0x482F_FFFF 508KB Reserved(1)
0x4830_0000 0x48FF_FFFF 13MB Reserved

2.9.3 DDR DMM TILER Extended Addressing Map

The TILER includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access the frame buffer in rotated and mirrored views. shows the details of the TILER Extended Address Mapping. This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems. However, other masters can access any one single view through the 512-MB TILER region in the base 4GByte address memory map.

Table 2-6 DDR DMM TILER Extended Address Mapping

BLOCK NAME START ADDRESS
(HEX)		 END ADDRESS
(HEX)		 SIZE DESCRIPTION
TILER View 0 0x1 0000_0000 0x1 1FFF_FFFF 512MB Natural 0° View
TILER View 1 0x1 2000_0000 0x1 3FFF_FFFF 512MB 0° with Vertical Mirror View
TILER View 2 0x1 4000_0000 0x1 5FFF_FFFF 512MB 0° with Horizontal Mirror View
TILER View 3 0x1 6000_0000 0x1 7FFF_FFFF 512MB 180° View
TILER View 4 0x1 8000_0000 0x1 9FFF_FFFF 512MB 90° with Vertical Mirror View
TILER View 5 0x1 A000_0000 0x1 BFFF_FFFF 512MB 270° View
TILER View 6 0x1 C000_0000 0x1 DFFF_FFFF 512MB 90° View
TILER View 7 0x1 E000_0000 0x1 FFFF_FFFF 512MB 90° with Horizontal Mirror View