JAJSEW3A
May 2017 – October 2018
AWR1443
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
改訂履歴
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Signal Descriptions
Table 4-1
Signal Descriptions
4.3
Pin Multiplexing
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power-On Hours (POH)
5.4
Recommended Operating Conditions
5.5
Power Supply Specifications
5.6
Power Consumption Summary
5.7
RF Specification
5.8
Thermal Resistance Characteristics for FCBGA Package [ABL0161]
5.9
Timing and Switching Characteristics
5.9.1
Power Supply Sequencing and Reset Timing
5.9.2
Synchronized Frame Triggering
5.9.3
Input Clocks and Oscillators
5.9.3.1
Clock Specifications
5.9.4
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
5.9.4.1
Peripheral Description
5.9.4.2
MibSPI Transmit and Receive RAM Organization
Table 5-7
SPI Timing Conditions
Table 5-8
SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
Table 5-9
SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
5.9.4.3
SPI Slave Mode I/O Timings
Table 5-10
SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
5.9.4.4
Typical Interface Protocol Diagram (Slave Mode)
5.9.5
LVDS Interface Configuration
5.9.5.1
LVDS Interface Timings
5.9.6
General-Purpose Input/Output
Table 5-12
Switching Characteristics for Output Timing versus Load Capacitance (CL)
5.9.7
Controller Area Network Interface (DCAN)
Table 5-13
Dynamic Characteristics for the DCANx TX and RX Pins
5.9.8
Serial Communication Interface (SCI)
Table 5-14
SCI Timing Requirements
5.9.9
Inter-Integrated Circuit Interface (I2C)
Table 5-15
I2C Timing Requirements
5.9.10
Quad Serial Peripheral Interface (QSPI)
Table 5-16
QSPI Timing Conditions
Table 5-17
Timing Requirements for QSPI Input (Read) Timings
Table 5-18
QSPI Switching Characteristics
5.9.11
JTAG Interface
Table 5-19
JTAG Timing Conditions
Table 5-20
Timing Requirements for IEEE 1149.1 JTAG
Table 5-21
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
External Interfaces
6.4
Subsystems
6.4.1
RF and Analog Subsystem
6.4.1.1
Clock Subsystem
6.4.1.2
Transmit Subsystem
6.4.1.3
Receive Subsystem
6.4.1.4
Radio Processor Subsystem
6.4.2
Master (Control) System
6.4.3
Host Interface
6.5
Accelerators and Coprocessors
6.6
Other Subsystems
6.6.1
ADC Channels (Service) for User Application
Table 6-3
GP-ADC Parameter
6.7
Identification
6.8
Boot Modes
6.8.1
Flashing Mode
6.8.2
Functional Mode
7
Applications, Implementation, and Layout
7.1
Application Information
7.2
Short-Range Radar
7.3
Blind Spot Detector and Ultrasonic Upgrades
7.4
Reference Schematic
7.5
Layout
7.5.1
Layout Guidelines
7.5.2
Stackup Details
8
Device and Documentation Support
8.1
Device Nomenclature
8.2
Tools and Software
8.3
Documentation Support
8.4
Community Resources
8.5
商標
8.6
静電気放電に関する注意事項
8.7
Export Control Notice
8.8
Glossary
9
Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ABL|161
MPBGAL4A
サーマルパッド・メカニカル・データ
発注情報
jajsew3a_oa
1
デバイスの概要